公开(公告)号：US10366199B2

公开(公告)日：2019-07-30

申请号：US15484615

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jagadish Hosmani ,  Mohammed Yousuff Shariff ,  Venugopal Sanaka ,  Huibo Hou

IPC: H02J3/00 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

公开(公告)号：US20180293344A1

公开(公告)日：2018-10-11

申请号：US15484615

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jagadish Hosmani ,  Mohammed Yousuff Shariff ,  Venugopal Sanaka ,  Huibo Hou

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/78 ,  H01L23/5286 ,  H01L27/0207 ,  H02J3/00

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

公开(公告)号：US11250197B1

公开(公告)日：2022-02-15

申请号：US17079727

申请日：2020-10-26

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar Lakshmipathi ,  Venugopal Sanaka ,  Babu Suriamoorthy ,  Madan Krishnappa ,  Pavan Kumar Patibanda

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/347 ,  G06F30/394 ,  G06F115/06 ,  G06F115/10 ,  G06F115/02 ,  G06F119/06

Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.