公开(公告)号：US10395993B2

公开(公告)日：2019-08-27

申请号：US15284567

申请日：2016-10-04

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Balaji Kannan ,  Siddarth Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/225 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

公开(公告)号：US10079182B2

公开(公告)日：2018-09-18

申请号：US14996575

申请日：2016-01-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US20170358655A1

公开(公告)日：2017-12-14

申请号：US15176902

申请日：2016-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/30608 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of forming the same include forming a work function stack over semiconductor fins in a first region and a second region, the work function stack having a bottom layer, a middle layer, and a top layer. The work function stack is etched to remove the top layer and to decrease a thickness of the middle layer in the second region, leaving a portion of the middle layer and the bottom layer intact. A gate is formed over the semiconductor fins in the first and second regions.

公开(公告)号：US09799656B2

公开(公告)日：2017-10-24

申请号：US15397042

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US09613870B2

公开(公告)日：2017-04-04

申请号：US14755829

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Oleg Gluschenkov ,  Balaji Kannan ,  Unoh Kwon

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L21/28 ,  H01L21/263

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

公开(公告)号：US09583400B1

公开(公告)日：2017-02-28

申请号：US14996563

申请日：2016-01-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

Abstract translation: 一种用于制造半导体器件的栅极堆叠的方法，包括在器件的沟道区上形成第一介电层，在第一介电层上形成阻挡层，在阻挡层上形成第一栅极金属层，形成覆盖层 在第一栅极金属层之上，去除阻挡层，第一栅极金属层和覆盖层的部分，以暴露栅极堆叠的p型场效应晶体管（pFET）区域中的第一介电层的一部分， 在所述覆盖层和所述第一介电层的暴露部分上沉积第一氮化物层，在所述第一氮化物层上沉积清除层，在所述扫气层上沉积第二氮化物层，以及在所述第二氮化物层上沉积栅电极材料。

公开(公告)号：US20170025315A1

公开(公告)日：2017-01-26

申请号：US15284567

申请日：2016-10-04

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Balaji Kannan ,  Siddarth Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC: H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49 ,  H01L21/225 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

Abstract translation: 一种用于形成与N-FET和P-FET栅极共用单个功函数金属的替代金属栅极结构的方法。 该方法分别使用单个光刻步骤来掺杂N-FET和P-FET栅极的高k材料。 掺杂允许使用单个功函金属，其又在金属栅极开口中提供更多的空间，使得块体填充材料可占据更多开口的体积，导致较低电阻门。

公开(公告)号：US20160049337A1

公开(公告)日：2016-02-18

申请号：US14919796

申请日：2015-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/311 ,  H01L21/225 ,  H01L21/033 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

公开(公告)号：US20160035841A1

公开(公告)日：2016-02-04

申请号：US14881766

申请日：2015-10-13

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/40 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

公开(公告)号：US20160027893A1

公开(公告)日：2016-01-28

申请号：US14875049

申请日：2015-10-05

Applicant: International Business Machines Corporation

Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

IPC: H01L29/51 ,  H01L29/423

CPC classification number: H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.