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    Thin Film Transistor and Manufacturing Method Thereof, and Array Substrate and Electronic Device
    62.
    发明申请
    Thin Film Transistor and Manufacturing Method Thereof, and Array Substrate and Electronic Device 有权

    公开(公告)号：US20230015871A1

    公开(公告)日：2023-01-19

    申请号：US17780877

    申请日：2021-05-27

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Jie Huang ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Jiayu He ,  Nianqi Yao ,  Feng Qu ,  Xiaochun Xu

    IPC: H01L29/786 ,  H01L27/12

    Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and an electronic device arc provided. The thin film transistor includes an active layer including multiple oxide layers which includes a channel layer, a transition layer and a first barrier layer, the channel layer is an layer with a highest carrier mobility, the channel layer is a crystalline or amorphous oxide layer, the transition layer is in direct contact with the channel layer, the first barrier layer is an outermost oxide layer, the first barrier layer and the transition layer are both crystalline oxide layers; a crystallization degree of the first barrier layer and a crystallization degree of the transition layer are greater than a crystallization degree of the channel layer, and a band gap of the first barrier layer and a band gap of the transition layer are larger than a band gap of the channel layer.

    MICRO-CHANNEL STRUCTURE, SENSOR, MICRO-FLUIDIC DEVICE, LAB-ON-CHIP DEVICE, AND METHOD OF FABRICATING MICRO-CHANNEL STRUCTURE
    64.
    发明申请
    MICRO-CHANNEL STRUCTURE, SENSOR, MICRO-FLUIDIC DEVICE, LAB-ON-CHIP DEVICE, AND METHOD OF FABRICATING MICRO-CHANNEL STRUCTURE 有权

    公开(公告)号：US20210331167A1

    公开(公告)日：2021-10-28

    申请号：US16475035

    申请日：2018-08-01

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Song Liu

    IPC: B01L3/00 ,  G01N27/414

    Abstract: The present application provides a micro-channel structure. The micro-channel structure includes a base substrate; a rail layer on the base substrate and including a first rail and a second rail spaced apart from each other; and a wall layer on a side of the rail layer distal to the base substrate, and including a first wall and a second wall at least partially spaced apart from each other, thereby forming a micro-channel between the first wall and the second wall. The micro-channel has an extension direction along a plane substantially parallel to a main surface of the base substrate, the extension direction being substantially parallel to extension directions of the first rail and the second rail along the plane substantially parallel to the main surface of the base substrate.

    Array substrate and manufacturing method thereof, and display device
    65.
    发明授权
    Array substrate and manufacturing method thereof, and display device 有权

    公开(公告)号：US11133363B2

    公开(公告)日：2021-09-28

    申请号：US16556342

    申请日：2019-08-30

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Ke Wang ,  Xinhong Lu ,  Hehe Hu ,  Wei Yang ,  Ce Ning

    IPC: H01L27/32 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

    Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.

    Display panel and manufacturing method thereof, driving method and display device
    66.
    发明授权
    Display panel and manufacturing method thereof, driving method and display device 有权

    公开(公告)号：US11092866B2

    公开(公告)日：2021-08-17

    申请号：US16631331

    申请日：2019-07-18

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Hehe Hu ,  Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Xin Gu

    IPC: G02F1/1368 ,  G02F1/1362

    Abstract: The present disclosure provides a display panel and a manufacturing method thereof, a driving method and a display device. The display panel includes: a base substrate and a thin film transistor on a surface of the base substrate. The thin film transistor includes: a gate, and a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain. a space region in which liquid crystal molecules are filled is formed in the first passivation layer. The space region is between the source and the drain. The source and the drain are configured to control rotation of the liquid crystal molecules.

    MICRO-CHANNEL DEVICE AND MANUFACTURING METHOD THEREOF AND MICRO-FLUIDIC SYSTEM
    67.
    发明申请
    MICRO-CHANNEL DEVICE AND MANUFACTURING METHOD THEREOF AND MICRO-FLUIDIC SYSTEM 有权

    公开(公告)号：US20210220824A1

    公开(公告)日：2021-07-22

    申请号：US16755911

    申请日：2019-04-16

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Ce Ning ,  Xiaochen Ma ,  Hehe Hu ,  Guangcai Yuan ,  Xin Gu

    IPC: B01L3/00

    Abstract: The present disclosure relates to a micro-channel device. The micro-channel device may include a micro-channel structure and a semiconductor junction. The micro-channel structure may include a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns. The cover layer and the base layer are configured to form a plurality of micro-channels. The semiconductor junction may include a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer stacked in a first direction.

    Oxide thin film transistor, array substrate, and preparation methods thereof
    68.
    发明授权
    Oxide thin film transistor, array substrate, and preparation methods thereof 有权

    公开(公告)号：US10916662B2

    公开(公告)日：2021-02-09

    申请号：US16528622

    申请日：2019-08-01

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Feng Guan ,  Guangcai Yuan ,  Zhi Wang ,  Chen Xu ,  Qi Yao ,  Zhanfeng Cao ,  Ce Ning ,  Woobong Lee ,  Lei Chen

    IPC: H01L29/786 ,  H01L27/12

    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.

    Array substrate and preparation method therefor, and display apparatus
    69.
    发明授权
    Array substrate and preparation method therefor, and display apparatus 有权

    公开(公告)号：US10795478B2

    公开(公告)日：2020-10-06

    申请号：US16319982

    申请日：2018-05-14

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Wenlin Zhang ,  Wei Yang ,  Ce Ning

    IPC: G06F3/041 ,  H01L27/12

    Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.

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