公开(公告)号：US20130196269A1

公开(公告)日：2013-08-01

申请号：US13362297

申请日：2012-01-31

申请人： Donald R. Preuss ,  Mitchell S. Burberry

发明人： Donald R. Preuss ,  Mitchell S. Burberry

IPC分类号： G03F7/20 ,  B05D5/12 ,  B05D3/02 ,  B05D3/06

CPC分类号： G06F3/044 ,  C23C18/04 ,  C23C18/06 ,  C23C18/08 ,  C23C18/14 ,  H05K1/095 ,  H05K3/1283 ,  H05K3/246 ,  H05K3/381 ,  H05K3/386 ,  H05K2203/0191 ,  H05K2203/0508 ,  H05K2203/0514 ,  H05K2203/072 ,  H05K2203/097 ,  H05K2203/102 ,  H05K2203/108 ,  H05K2203/1194 ,  H05K2203/125 ,  H05K2203/1383 ,  H05K2203/1572

摘要： A method of improving conductivity of a metal pattern (18) includes providing a developed silver pattern (14) formed from a photographic silver salt provided in a binder coated on a substrate (12); and selectively heating the silver pattern with electromagnetic radiation.

摘要翻译： 提高金属图案（18）的导电性的方法包括提供由涂覆在基材（12）上的粘合剂中提供的照相银盐形成的显影银图案（14）。 并用电磁辐射选择性地加热银色图案。

公开(公告)号：US20130192882A1

公开(公告)日：2013-08-01

申请号：US13750801

申请日：2013-01-25

申请人： KYOCERA SLC Technologies Corporation

发明人： Takayuki NEJIME ,  Masaaki HARAZONO ,  Yoshihiro HOSOI

IPC分类号： H05K1/03

CPC分类号： H05K1/038 ,  H01L2224/16225 ,  H05K1/036 ,  H05K3/0044 ,  H05K2203/025 ,  H05K2203/1572

摘要： A wiring board of the present invention includes a substrate including a woven fabric formed of a plurality of glass fibers and a resin covering the woven fabric; a plurality of through holes T penetrating through the substrate in a thickness direction thereof; and a plurality of through hole conductors adhered to inner walls of the through holes T respectively. The through holes T include a first through hole and a second through hole, and, in the woven fabric, the number of the glass fibers through which the first through hole penetrates is larger than the number of the glass fibers through which the second through hole penetrates. In the first and second through holes, portions thereof having narrowest widths are surrounded by the woven fabric, and the narrow width portion of the first through hole is smaller than the narrow width portion of the second through hole.

摘要翻译： 本发明的布线基板包括：基材，其具有由多根玻璃纤维形成的织布和覆盖该织物的树脂; 多个通孔T，其贯穿基板的厚度方向; 以及多个通孔导体分别粘附到通孔T的内壁。 通孔T包括第一通孔和第二通孔，并且在机织织物中，第一通孔穿过的玻璃纤维的数量大于第二通孔所通过的玻璃纤维的数量 渗透 在第一和第二通孔中，具有最窄宽度的部分被织物包围，并且第一通孔的窄宽度部分小于第二通孔的窄宽度部分。

公开(公告)号：US08465466B2

公开(公告)日：2013-06-18

申请号：US10996026

申请日：2004-11-22

申请人： Michael E. Miller ,  Rajiv Shah

发明人： Michael E. Miller ,  Rajiv Shah

IPC分类号： A61M31/00 ,  A61K9/22

CPC分类号： A61B5/145 ,  A61B5/0006 ,  A61B5/0031 ,  A61B5/14532 ,  A61B5/6882 ,  A61B17/3468 ,  A61M1/1698 ,  A61M5/14276 ,  A61M2230/20 ,  A61M2230/201 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

摘要： A method and system for non-vascular sensor implantation. An implant unit is implanted in an area of a body and a foreign body capsule is allowed to form around the area of the implant unit. The sensor may be directed into a body cavity such as, for example, the peritoneal space, subcutaneous tissues, the foreign body capsule, or other area of the body. A subcutaneous area of the body may be tunneled to place the sensor. The system may include an implant unit such as, for example, for delivering drug to a human body and a sensor for detecting a physiological parameter. The sensor may be separate from and connectable to the implant unit and may be placed in a non-vascular area of the human body.

公开(公告)号：US08446386B2

公开(公告)日：2013-05-21

申请号：US13235321

申请日：2011-09-16

申请人： Mark Arthur Hamblin ,  Steve Porter Hotelling

发明人： Mark Arthur Hamblin ,  Steve Porter Hotelling

IPC分类号： G09G5/00

CPC分类号： H01R12/62 ,  G06F3/0416 ,  G06F2203/04103 ,  H01H2001/5816 ,  H01R4/04 ,  H01R43/205 ,  H05K3/323 ,  H05K3/361 ,  H05K2203/0278 ,  H05K2203/1121 ,  H05K2203/1572 ,  Y10T29/49124 ,  Y10T29/49155

摘要： A multi-touch sensor panel can be created using a substrate with column and row traces formed on either side. Metal traces running along the border of the substrate can be used to bring the row traces to the same edge as the column traces. A single flex circuit can be fabricated to connect to the rows and columns on directly opposing sides. Flex printed circuits can be bonded to directly opposing attachment areas of a substrate by cooling one side of the substrate while bonding the other. In addition, “coverlay” material extending over right-angled traces on the flex circuit ensure that those traces do not get shorted should conductive bonding material get squeezed out during bonding. Furthermore, a spacer is placed at the distal end of the flex circuit to apply even bonding pressure over the entire flex circuit attachment area during bonding.

摘要翻译： 可以使用在两侧形成的柱和行迹线的基板来创建多点触摸传感器面板。 可以使用沿基板边界延伸的金属轨迹将行迹线与列轨迹相同。 可以制造单个柔性电路以连接到直接相对侧上的行和列。 柔性印刷电路可以通过在粘合另一个基板的同时冷却基板的一侧而与基板的直接相对的附接区域接合。 此外，在柔性电路上的直角迹线上延伸的“覆盖层”材料可确保在接合期间导电接合材料被挤出时，这些迹线不会短路。 此外，间隔件放置在柔性电路的远端处，以在接合期间在整个柔性电路连接区域上施加均匀的粘结压力。

公开(公告)号：US08438515B2

公开(公告)日：2013-05-07

申请号：US13339525

申请日：2011-12-29

申请人： Michael W. Leddige ,  Kuljit Singh Bains ,  John Thomas Sprietsma

发明人： Michael W. Leddige ,  Kuljit Singh Bains ,  John Thomas Sprietsma

IPC分类号： G06F17/50

CPC分类号： H01L23/49816 ,  G11C5/02 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.

摘要翻译： 存储器模块具有连接阵列。 连接阵列以行和列排列，使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。 还公开并要求保护其他实施例。

公开(公告)号：US20130098662A1

公开(公告)日：2013-04-25

申请号：US13644888

申请日：2012-10-04

申请人： Fujikura Ltd.

发明人： Yuji Inatani

IPC分类号： H05K1/02 ,  H05K3/00

CPC分类号： H05K3/4697 ,  H05K3/4611 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/0228 ,  H05K2203/0264 ,  H05K2203/1572 ,  Y10T29/49124 ,  Y10T29/49144

摘要： A multi-layer circuit board having a connector portion of an inner layer substrate being exposed, the multi-layer circuit board comprising: an inner layer substrate in which an inner layer circuit is formed, the inner layer circuit including the connector portion; and an outer layer substrate having an outer layer circuit formed on an insulating layer and having a region corresponding to the connector portion peeled off, an inner layer circuit side of the inner layer substrate and an insulating layer side of the outer layer substrate being adhered to one another via an adhesive layer so as to face one another, and a conductor layer other than the connector portion of the inner layer circuit being adhered to the outer layer substrate directly by the adhesive layer.

摘要翻译： 一种具有内层基板的连接部分露出的多层电路板，所述多层电路板包括：形成有内层电路的内层基板，所述内层电路包括所述连接器部分; 以及外层基板，其具有形成在绝缘层上并且具有与所述连接器部分剥离的区域相对应的区域的外层电路，所述内层基板的内层电路侧和所述外层基板的绝缘层侧被粘附到 通过粘合剂层彼此面对，并且除了内层电路的连接器部分之外的导体层直接通过粘合剂层粘附到外层基板。

公开(公告)号：US08411458B2

公开(公告)日：2013-04-02

申请号：US12784549

申请日：2010-05-21

申请人： Kwang-soo Park ,  Kyung-suk Kim

发明人： Kwang-soo Park ,  Kyung-suk Kim

IPC分类号： H05K7/00

CPC分类号： G06F1/16 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0295 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/0949 ,  H05K2201/10015 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K2203/1572

摘要： An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.

公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC分类号： H01L23/495

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US20130043063A1

公开(公告)日：2013-02-21

申请号：US13642471

申请日：2011-03-02

申请人： Yoichi Saito ,  Shigeru Michiwaki ,  Noriaki Taneko ,  Shukichi Takii

发明人： Yoichi Saito ,  Shigeru Michiwaki ,  Noriaki Taneko ,  Shukichi Takii

IPC分类号： B32B38/10 ,  H05K1/02 ,  B32B38/08

CPC分类号： H05K3/205 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/1572

摘要： A method of producing a printed circuit board includes: forming a metal layer on a support plate; forming a mask layer on the metal layer; forming a pattern plating having a stem as plating up to a level of the mask layer, and a cap as a portion of plating exceeding the mask layer and having an outgrowth lying over the surface of the mask layer; laminating an insulating base on a conductive circuit board constituted by the support plate, the metal layer and the pattern plating to form a circuit board intermediate in which the pattern plating is buried in the base; removing the support plate and the metal layer to form an exposed surface; and mechanically polishing the exposed surface until the stem of the pattern plating is removed, to increase the width of the conductive pattern on the exposed surface.

摘要翻译： 制造印刷电路板的方法包括：在支撑板上形成金属层; 在所述金属层上形成掩模层; 形成具有作为所述掩模层的水平的电极的杆的图案电镀，以及超过所述掩模层并且具有位于所述掩模层的表面上的生长的作为电镀部分的帽; 在由支撑板，金属层和图案电镀构成的导电电路板上层叠绝缘基底，以形成电路板中间，其中图案电镀埋在基座中; 移除支撑板和金属层以形成暴露表面; 并且机械抛光露出的表面，直到去除图案电镀的杆，以增加暴露表面上的导电图案的宽度。

公开(公告)号：US08378481B2

公开(公告)日：2013-02-19

申请号：US13420341

申请日：2012-03-14

申请人： Frank Lambrecht

发明人： Frank Lambrecht

IPC分类号： H01L23/34 ,  H01L21/00

CPC分类号： H01L23/48 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00

摘要： The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

摘要翻译： 半导体模块包括在衬底的第一侧上的多个存储器管芯和在衬底的第二侧上的多个缓冲管芯。 每个存储器管芯相对设置并电耦合到缓冲管芯之一。