公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

发明人： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC分类号： H01L23/495

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US08361838B2

公开(公告)日：2013-01-29

申请号：US13241812

申请日：2011-09-23

申请人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

摘要： A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

摘要翻译： 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US20120171803A1

公开(公告)日：2012-07-05

申请号：US13412821

申请日：2012-03-06

申请人： Seung Taek YANG

发明人： Seung Taek YANG

IPC分类号： H01L31/18

CPC分类号： H01L27/14645 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

摘要： A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer.

摘要翻译： 反向图像传感器模块包括第一和第二半导体芯片，以及第一和第二绝缘层。 第一半导体芯片包括具有第一表面和背离第一表面的第二表面的第一半导体芯片本体，设置在第一表面上的光电二极管和布置在第二表面上并具有电连接到光电二极管的布线层的布线层 以及电连接到布线的接合焊盘。 第二半导体芯片包括具有面向布线层的第三表面的第二半导体芯片本体，以及与焊盘电连接并穿过第二半导体芯片主体的通孔。 第一绝缘层设置在布线层上，第二绝缘层设置在与第一绝缘层相对的第二半导体芯片主体的第三表面上，并与第一绝缘层接合。

公开(公告)号：US08018043B2

公开(公告)日：2011-09-13

申请号：US12261112

申请日：2008-10-30

申请人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

发明人： Min Suk Suh ,  Seung Taek Yang ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/4334 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311

摘要： A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

摘要翻译： 半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。 形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。 再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。 第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面 。 在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。

公开(公告)号：US20110121420A1

公开(公告)日：2011-05-26

申请号：US12647648

申请日：2009-12-28

申请人： Seung Taek YANG

发明人： Seung Taek YANG

IPC分类号： H01L31/14 ,  H01L31/18 ,  H01L31/0232

CPC分类号： H01L27/14645 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

摘要： A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer.

摘要翻译： 反向图像传感器模块包括第一和第二半导体芯片，以及第一和第二绝缘层。 第一半导体芯片包括具有第一表面和背离第一表面的第二表面的第一半导体芯片本体，设置在第一表面上的光电二极管和布置在第二表面上并具有电连接到光电二极管的布线层的布线层 以及电连接到布线的接合焊盘。 第二半导体芯片包括具有面向布线层的第三表面的第二半导体芯片本体，以及与焊盘电连接并穿过第二半导体芯片主体的通孔。 第一绝缘层设置在布线层上，第二绝缘层设置在与第一绝缘层相对的第二半导体芯片主体的第三表面上，并与第一绝缘层接合。

公开(公告)号：US20090121326A1

公开(公告)日：2009-05-14

申请号：US11953967

申请日：2007-12-11

申请人： Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

发明人： Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

IPC分类号： H01L23/495 ,  H01L23/538

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

摘要： A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

摘要翻译： 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US07498199B2

公开(公告)日：2009-03-03

申请号：US11777368

申请日：2007-07-13

申请人： Seung Taek Yang

发明人： Seung Taek Yang

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83886 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package includes the steps of: forming a material layer containing conductive particles on a semiconductor chip having a plurality of bonding pads on the upper surface thereof, baking the material layers to a non-flowing state; attaching the semiconductor chip in a face down manner to a substrate having connecting pads on the location corresponding to the bonding pads by using the material layers containing conductive particles; applying voltage for a electrical signal exchange to the semiconductor chip and the substrate so that the conductive particles are gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate; and curing the conductive particles of the material layers so that the conductive particles gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate to an non-flowing state.

摘要翻译： 一种制造半导体封装的方法，包括以下步骤：在其上表面具有多个焊盘的半导体芯片上形成含有导电颗粒的材料层，将材料层烧成非流动状态; 通过使用含有导电颗粒的材料层，将半导体芯片以面朝下的方式附接到具有在与焊盘对应的位置处的连接焊盘的基板; 将电压施加到半导体芯片和衬底的电信号交换，使得导电颗粒聚集在半导体芯片的焊盘和衬底的连接焊盘之间; 以及固化所述材料层的导电颗粒，使得所述导电颗粒聚集在所述半导体芯片的焊盘和所述衬底的所述连接焊盘之间为非流动状态。

公开(公告)号：US20080001283A1

公开(公告)日：2008-01-03

申请号：US11679268

申请日：2007-02-27

申请人： Ha Na LEE ,  Seung Taek YANG

发明人： Ha Na LEE ,  Seung Taek YANG

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L23/367 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A stack package includes a base substrate having connection pads on an upper surface thereof and ball lands on a lower surface thereof; at least two semiconductor chips stacked by intervening a spacer on the base substrate and defined with through-holes for electrical connections on positions corresponding to the connection pads; electrical connection members for electrically connecting the stacked semiconductor chips and the base substrate to each other; a pair of heat sinks formed such that they contact the side surfaces of the stacked semiconductor chips and extend in a direction perpendicular to the base substrate; and outside connection terminals attached to the ball lands located on the lower surface of the base substrate.

摘要翻译： 堆叠封装包括在其上表面上具有连接焊盘的基底基板，并且在其下表面上具有焊盘; 至少两个半导体芯片通过在基底衬底上插入间隔物并且与对应于连接焊盘的位置上的用于电气连接的通孔间隔开来堆叠; 用于将堆叠的半导体芯片和基底基板彼此电连接的电连接构件; 一对散热片形成为使得它们接触堆叠的半导体芯片的侧表面并且在垂直于基底基板的方向上延伸; 以及附接到位于基底基板的下表面上的球接头的外部连接端子。

公开(公告)号：US08502366B2

公开(公告)日：2013-08-06

申请号：US13339073

申请日：2011-12-28

申请人： Seung Taek Yang

发明人： Seung Taek Yang

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/014

摘要： A semiconductor package includes a body having a first surface and a second surface facing away from the first surface, and formed with a groove in the first surface. First connection parts may electrically connect a portion of the first surface to a portion of the second surface of the body. Second connection parts may electrically connect a portion of a bottom portion of the groove to a portion of the second surface of the body. A lower device may be disposed in the groove of the body, and have third connection parts that are electrically connected with the second connection parts. An upper device may be disposed on the body and the lower device, and have fourth connection parts that are electrically connected with the first connection parts and the third connection parts.

摘要翻译： 半导体封装包括具有第一表面和背离第一表面的第二表面的主体，并且在第一表面中形成有凹槽。 第一连接部件可将第一表面的一部分电连接到主体的第二表面的一部分。 第二连接部件可将槽的底部的一部分电连接到主体的第二表面的一部分。 下部装置可以设置在主体的槽中，并且具有与第二连接部分电连接的第三连接部。 上部装置可以设置在主体和下部装置上，并且具有与第一连接部和第三连接部电连接的第四连接部。

公开(公告)号：US20120299169A1

公开(公告)日：2012-11-29

申请号：US13569600

申请日：2012-08-08

申请人： Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

发明人： Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

IPC分类号： H01L25/07

CPC分类号： H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2224/19 ,  H01L2924/00

摘要： A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

摘要翻译： 堆叠的晶片级封装包括具有第一焊盘的第一半导体芯片和具有第二焊盘的第二半导体芯片。 半导体芯片的两个接合焊盘面向相同的方向。 第二半导体芯片与第一半导体芯片平行设置。 第三半导体芯片设置在用作支撑衬底的第一和第二半导体芯片上。 第三半导体芯片具有在附接时在第一和第二半导体芯片之间露出的第三焊盘。 最后，再分布结构电连接到第一，第二和第三键合焊盘。