公开(公告)号：US20240114794A1

公开(公告)日：2024-04-04

申请号：US18484311

申请日：2023-10-10

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Hardik Bhupendra MODI ,  Adarsh Karan JAISWAL ,  Anil K. AGARWAL ,  Engin Ibrahim PEHLIVANOGLU

IPC: H10N30/071 ,  H01L23/552 ,  H01L23/66 ,  H03F3/195 ,  H03H9/02 ,  H03H9/64

CPC classification number: H10N30/071 ,  H01L23/552 ,  H01L23/66 ,  H03F3/195 ,  H03H9/02976 ,  H03H9/6406 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/15313 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03F2200/294

Abstract: Devices and methods related to stack assembly. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.

公开(公告)号：US11894345B2

公开(公告)日：2024-02-06

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/08 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06586 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/3025

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20230387079A1

公开(公告)日：2023-11-30

申请号：US17825695

申请日：2022-05-26

Applicant: Micron Technology, Inc.

Inventor： Chong Leong Gan

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.

公开(公告)号：US20190079133A1

公开(公告)日：2019-03-14

申请号：US16125096

申请日：2018-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre SARAFIANOS ,  Thomas ORDAS

IPC: G01R31/12 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  G01R31/317

CPC classification number: G01R31/1272 ,  G01R31/31719 ,  G06K19/073 ,  H01L23/5386 ,  H01L23/5388 ,  H01L23/573 ,  H01L23/576 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06541

Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.

公开(公告)号：US20180374805A1

公开(公告)日：2018-12-27

申请号：US16121467

申请日：2018-09-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin YEH ,  Jen-Chieh KAO ,  Chih-Yi HUANG ,  Fu-Chen CHU

IPC: H01L23/66 ,  H01L43/02 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L23/49838 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L43/02 ,  H01L2223/6605 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

公开(公告)号：US20180228028A1

公开(公告)日：2018-08-09

申请号：US15945913

申请日：2018-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/34 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46 ,  H05K1/14 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US20180226365A1

公开(公告)日：2018-08-09

申请号：US15425723

申请日：2017-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin YEH ,  Jen-Chieh KAO ,  Chih-Yi HUANG ,  Fu-Chen CHU

IPC: H01L23/66 ,  H01L23/498 ,  H01L43/02

CPC classification number: H01L43/02 ,  H01L23/49838 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

公开(公告)号：US20180182714A1

公开(公告)日：2018-06-28

申请号：US15845256

申请日：2017-12-18

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： De Jun HUANG ,  Quan Bang LI

IPC: H01L23/552 ,  H01L49/02 ,  H01L21/56 ,  H01L21/28 ,  H01L23/28 ,  H01L23/13 ,  H01L23/00 ,  H05K1/02 ,  G11C16/04 ,  G11C17/08

CPC classification number: H01L23/552 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L21/561 ,  H01L23/13 ,  H01L23/28 ,  H01L24/97 ,  H01L25/0657 ,  H01L49/02 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06575 ,  H05K1/0237

Abstract: The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.

公开(公告)号：US20180151485A1

公开(公告)日：2018-05-31

申请号：US15362548

申请日：2016-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jen-Chieh KAO ,  Chang-Lin YEH ,  Yi CHEN ,  Sung-Hung CHIANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/02 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/02 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

公开(公告)号：US09935083B2

公开(公告)日：2018-04-03

申请号：US15149144

申请日：2016-05-08

Applicant: Amkor Technology, Inc.

Inventor： Jae Ung Lee ,  Yung Woo Lee ,  Mi Kyeong Choi ,  Jin Seong Kim

IPC: H01L23/552 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.