公开(公告)号：US4949455A

公开(公告)日：1990-08-21

申请号：US305312

申请日：1989-02-01

Applicant: Keiichi Nakamura ,  Tsutomu Oshima ,  Noriharu Kurokawa ,  Toshihiko Kitai

Inventor： Keiichi Nakamura ,  Tsutomu Oshima ,  Noriharu Kurokawa ,  Toshihiko Kitai

IPC: H01L21/48 ,  H01L23/49 ,  H01L23/498 ,  H01R43/16 ,  H05K3/40

CPC classification number: H05K3/4038 ,  H01L21/4885 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2203/0235 ,  H05K3/4007 ,  Y10T29/49149 ,  Y10T29/49213

Abstract: An electrical pin comprises a metal pin having plated metal members at peripheral end surfaces thereof and head members including solder secured to the end surfaces of the metal pin and the plated metal members.

Abstract translation: 电引脚包括在其周边端面上具有镀金属部件的金属销，以及包括固定在金属销和电镀金属部件的端面上的焊料的头部件。

公开(公告)号：US4819131A

公开(公告)日：1989-04-04

申请号：US089530

申请日：1987-08-26

Applicant: Toshihiko Watari

Inventor： Toshihiko Watari

IPC: H01L21/48 ,  H01L23/12 ,  H01L23/50 ,  H01L23/52 ,  H01L23/538 ,  H05K3/46 ,  H05K1/14

CPC classification number: H01L21/4885 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: An integrated circuit package including a multilayer ceramic substrate for mounting a plurality of integrated circuit chips on a first surface thereof. The substrate is provided with a power supply layer, a ground connection layer and circuit patterns. An array of coaxial pins is juxtaposed on the opposite surface of the substrate. Each coaxial pin includes an inner conductor and an outer conductor. The inner conductor of one or more coaxial pins is connected to the power supply layer and the inner conductors of the remaining coaxial pins are connected to the circuit patterns. The outer conductors of all the coaxial pins are connected to the ground connection layer.

Abstract translation: 一种集成电路封装，包括用于在其第一表面上安装多个集成电路芯片的多层陶瓷基板。 基板设置有电源层，接地连接层和电路图案。 同轴销的阵列并置在基板的相对表面上。 每个同轴销包括内部导体和外部导体。 一个或多个同轴引脚的内导体连接到电源层，其余同轴引脚的内导体连接到电路图案。 所有同轴引脚的外导体连接到接地连接层。

公开(公告)号：US20240145350A1

公开(公告)日：2024-05-02

申请号：US18475318

申请日：2023-09-27

Applicant: MEDIATEK Inc.

Inventor： Pu-Shan HUANG ,  Chi-Yuan CHEN ,  Shih-Chin LIN

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L23/4952 ,  H01L21/4885 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48155 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/19101

Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.

公开(公告)号：US11824007B2

公开(公告)日：2023-11-21

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US11791271B2

公开(公告)日：2023-10-17

申请号：US17306331

申请日：2021-05-03

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L23/538 ,  H01L21/48 ,  H01L27/092

CPC classification number: H01L23/5383 ,  H01L21/4885 ,  H01L27/0924

Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

公开(公告)号：US11665889B2

公开(公告)日：2023-05-30

申请号：US17523439

申请日：2021-11-10

Applicant: Winbond Electronics Corp.

Inventor： Shuen-Hsiang Ke ,  Shih-Chieh Lin

IPC: H01L27/10 ,  H01L21/308 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L21/48

CPC classification number: H10B12/488 ,  H01L21/02362 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/4885 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H10B12/482

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

公开(公告)号：US10008392B2

公开(公告)日：2018-06-26

申请号：US15424995

申请日：2017-02-06

Applicant: Infineon Technologies AG

Inventor： Alexander Hoehn ,  Georg Borghoff

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/053 ,  H01L23/08 ,  H01L23/373 ,  H01L23/498 ,  H05K5/00

CPC classification number: H01L23/053 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/4885 ,  H01L21/52 ,  H01L23/08 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H05K5/0008 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power semiconductor module is produced by: providing an electrically conductive terminal block having a screw thread, a connecting conductor having first and second sections, a module housing, a circuit carrier having a dielectric insulation carrier and an upper metallization layer on an upper side of the insulation carrier, and a semiconductor component; fitting the semiconductor component on the circuit carrier; producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section; producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section; and arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing so the semiconductor component is arranged in the module housing and the screw thread is accessible from an outer side of the module housing.

公开(公告)号：US09966321B2

公开(公告)日：2018-05-08

申请号：US15335260

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang

IPC: H01L21/00 ,  H01L23/24 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/24 ,  H01L21/481 ,  H01L21/4885 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/181 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

公开(公告)号：US09783895B2

公开(公告)日：2017-10-10

申请号：US15206938

申请日：2016-07-11

Applicant: Advanced Silicon Group, Inc.

Inventor： Joanne Yim ,  Jeffrey B. Miller ,  Michael Jura ,  Marcie R. Black ,  Joanne Forziati ,  Brian P. Murphy ,  Adam Standley

IPC: C23F1/30 ,  H01L21/308 ,  H01L21/306 ,  H01L21/48 ,  H01L21/02 ,  H01L29/06 ,  H01L29/41 ,  C30B29/06 ,  C30B29/60 ,  H01M4/38 ,  H01M10/0525 ,  H01L35/10 ,  H01M4/04 ,  H01M4/134 ,  H01M4/02

CPC classification number: C23F1/30 ,  C30B29/06 ,  C30B29/60 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/4885 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/413 ,  H01L35/10 ,  H01L2924/0002 ,  H01M4/0426 ,  H01M4/134 ,  H01M4/386 ,  H01M10/0525 ,  H01M2004/027

Abstract: In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal.

公开(公告)号：US09775242B2

公开(公告)日：2017-09-26

申请号：US15005589

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Tsung-Yu Chen ,  Rebecca Shia

IPC: H01L23/488 ,  H01L21/60 ,  H05K1/11 ,  H01L23/48 ,  H05K3/10 ,  H01L21/48 ,  H05K5/00 ,  H01R13/04 ,  H01L23/498 ,  H05K3/40 ,  H01L23/373 ,  H05K3/34

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/4885 ,  H01L23/373 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01R13/04 ,  H05K3/103 ,  H05K3/3426 ,  H05K3/4015 ,  H05K5/0069 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10787 ,  H05K2201/10795 ,  H05K2201/1081 ,  H05K2203/1178 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.