公开(公告)号：US20160286642A1

公开(公告)日：2016-09-29

申请号：US15005589

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Tsung-Yu Chen ,  Rebecca Shia

IPC: H05K1/11 ,  H01L23/498 ,  H01L23/373 ,  H05K3/40

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/4885 ,  H01L23/373 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01R13/04 ,  H05K3/103 ,  H05K3/3426 ,  H05K3/4015 ,  H05K5/0069 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10787 ,  H05K2201/10795 ,  H05K2201/1081 ,  H05K2203/1178 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

公开(公告)号：US09775242B2

公开(公告)日：2017-09-26

申请号：US15005589

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Tsung-Yu Chen ,  Rebecca Shia

IPC: H01L23/488 ,  H01L21/60 ,  H05K1/11 ,  H01L23/48 ,  H05K3/10 ,  H01L21/48 ,  H05K5/00 ,  H01R13/04 ,  H01L23/498 ,  H05K3/40 ,  H01L23/373 ,  H05K3/34

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/4885 ,  H01L23/373 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01R13/04 ,  H05K3/103 ,  H05K3/3426 ,  H05K3/4015 ,  H05K5/0069 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10787 ,  H05K2201/10795 ,  H05K2201/1081 ,  H05K2203/1178 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

公开(公告)号：US20230253287A1

公开(公告)日：2023-08-10

申请号：US17668241

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Tsung-Yu Chen ,  Rebecca Shia

IPC: H01L23/373 ,  H01L23/522 ,  H01L23/528 ,  H01L21/48

CPC classification number: H01L23/3731 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/4807

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to efficient heat dissipation in integrated circuit implementations, such as three-dimensional packages, using integrated thermoresponsive materials. An integrated circuit die includes a thermoresponsive material in a via that extends through at least a portion of a device layer and one or more metal interconnect layers of the integrated circuit die. Such integrated circuit dies including thermoresponsive materials may be stacked vertically with their thermoresponsive material filled vias aligned.

公开(公告)号：US10524392B1

公开(公告)日：2019-12-31

申请号：US16146671

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Tsung-Yu Chen

IPC: H05K7/20 ,  C09K5/06

Abstract: A device can dissipate heat from an electrical component by using a phase change material. A horizontal circuitry layer can have opposing first and second sides. A vertical hole can extend through the horizontal circuitry layer. A vertical channel can include a phase change material positioned in the vertical hole and in thermal contact with the first and second sides of the horizontal circuitry layer. The phase change material can dissipate a first amount of heat from the first side by absorbing the first amount of heat and changing phase from a solid form to a liquid form. The phase change material, when in the liquid form, can dissipate a second amount of heat from the first side by transporting the second amount of heat via convection from the first side of the horizontal circuitry layer to the second side of the horizontal circuitry layer.