公开(公告)号：US20240387378A1

公开(公告)日：2024-11-21

申请号：US18787615

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US12113025B2

公开(公告)日：2024-10-08

申请号：US17881981

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Hsien-Wen Liu ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

公开(公告)号：US11996372B2

公开(公告)日：2024-05-28

申请号：US17372677

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0655 ,  H01Q1/2283 ,  H01L2223/6677

Abstract: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

公开(公告)号：US11855059B2

公开(公告)日：2023-12-26

申请号：US17808621

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US11824007B2

公开(公告)日：2023-11-21

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US11682599B2

公开(公告)日：2023-06-20

申请号：US16199535

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

公开(公告)号：US11610854B2

公开(公告)日：2023-03-21

申请号：US17222044

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/28 ,  H01Q9/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US11430776B2

公开(公告)日：2022-08-30

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11410982B2

公开(公告)日：2022-08-09

申请号：US17097301

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yi Yang ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683

Abstract: A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

公开(公告)号：US20220216192A1

公开(公告)日：2022-07-07

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.