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公开(公告)号：US12027414B2
公开(公告)日：2024-07-02
申请号：US17751895
申请日：2022-05-24
Inventor： Li-Zhen Yu , Cheng-Chi Chuang , Chih-Hao Wang , Yu-Ming Lin , Lin-Yu Huang
IPC: H01L21/768 , H01L23/522 , H01L29/417 , H01L29/66
CPC classification number: H01L21/76802 , H01L21/76831 , H01L23/5226 , H01L29/41775 , H01L29/66477
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.
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公开(公告)号：US20240215254A1
公开(公告)日：2024-06-27
申请号：US18602067
申请日：2024-03-12
Inventor： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong , Han-Jong Chia
CPC classification number: H10B51/10 , H01L23/5226 , H01L29/40111 , H01L29/516 , H01L29/66666 , H01L29/78391 , H10B51/20 , H10B51/30
Abstract: Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
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公开(公告)号：US11980036B2
公开(公告)日：2024-05-07
申请号：US17873207
申请日：2022-07-26
Inventor： Chao-I Wu , Yu-Ming Lin , Han-Jong Chia
CPC classification number: H10B53/00 , G11C5/06 , G11C11/221 , H10B51/00
Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
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公开(公告)号：US20240147738A1
公开(公告)日：2024-05-02
申请号：US18404103
申请日：2024-01-04
Inventor： Chao-I Wu , Yu-Ming Lin
CPC classification number: H10B63/34 , G11C7/18 , G11C8/14 , H01L23/5226 , H01L29/78391 , H10N70/061 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.
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公开(公告)号：US11963363B2
公开(公告)日：2024-04-16
申请号：US17163574
申请日：2021-02-01
Inventor： Han-Jong Chia , Meng-Han Lin , Yu-Ming Lin
CPC classification number: H10B51/20 , G11C11/2255 , G11C11/2257 , H10B51/10 , H10B51/40
Abstract: A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.
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Patent Agency Ranking
公开(公告)号：US20240113222A1
公开(公告)日：2024-04-04
申请号：US18149312
申请日：2023-01-03
Inventor： Yan-Yi Chen , Wu-Wei Tsai , Yu-Ming Hsiang , Hai-Ching Chen , Yu-Ming Lin , Chung-Te Lin
IPC: H01L29/786 , H01L27/07 , H01L29/66
CPC classification number: H01L29/78603 , H01L27/0705 , H01L29/66742
Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.
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公开(公告)号：US20240090230A1
公开(公告)日：2024-03-14
申请号：US18151483
申请日：2023-01-09
Inventor： Wen-Ling Lu , Chen-Jun Wu , Ya-Yun Cheng , Sheng-Chih Lai , Yi-Ching Liu , Yu-Ming Lin , Feng-Cheng Yang , Chung-Te Lin
CPC classification number: H10B51/30 , G11C11/223 , G11C11/2275 , H10B51/20
Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
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公开(公告)号：US11910615B2
公开(公告)日：2024-02-20
申请号：US17327752
申请日：2021-05-23
Inventor： Meng-Han Lin , Han-Jong Chia , Feng-Cheng Yang , Bo-Feng Young , Nuo Xu , Sai-Hooi Yeong , Yu-Ming Lin
Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.
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公开(公告)号：US11901238B2
公开(公告)日：2024-02-13
申请号：US17750895
申请日：2022-05-23
Inventor： Shih-Chuan Chiu , Jia-Chuan You , Chia-Hao Chang , Chun-Yuan Chen , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/768 , H01L23/522 , H01L29/06
CPC classification number: H01L21/823475 , H01L21/76829 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/5226 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/785
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.
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公开(公告)号：US11895849B2
公开(公告)日：2024-02-06
申请号：US17882845
申请日：2022-08-08
Inventor： Chao-I Wu , Yu-Ming Lin
IPC: H01L27/24 , H01L45/00 , H10B63/00 , H01L29/78 , H01L23/522 , G11C7/18 , G11C8/14 , H10N70/00 , H10N70/20
CPC classification number: H10B63/34 , G11C7/18 , G11C8/14 , H01L23/5226 , H01L29/78391 , H10N70/061 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.
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