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公开(公告)号：US20240049470A1
公开(公告)日：2024-02-08
申请号：US17818343
申请日：2022-08-08
Inventor： Chen-Jun Wu , Sun-Yi Chang , Sheng-Chih Lai , Chung-Te Lin
IPC: H01L27/11568 , H01L27/11521 , H01L27/1159 , H01L27/22 , H01L27/24 , G11C16/08 , G11C11/22 , G11C11/16 , G11C13/00
CPC classification number: H01L27/11568 , H01L27/11521 , H01L27/1159 , H01L27/228 , H01L27/2436 , G11C16/08 , G11C11/2257 , G11C11/1657 , G11C13/0028
Abstract: A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.
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公开(公告)号：US12035534B2
公开(公告)日：2024-07-09
申请号：US18308031
申请日：2023-04-27
Inventor： Chen-Jun Wu , Yu-Wei Jiang , Sheng-Chih Lai
IPC: H10B43/35 , H01L23/522 , H10B41/27 , H10B41/35 , H10B43/27
CPC classification number: H10B43/35 , H01L23/5226 , H10B41/27 , H10B41/35 , H10B43/27
Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.
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3.发明公开公开(公告)号：US20230328996A1
公开(公告)日：2023-10-12
申请号：US18334590
申请日：2023-06-14
Inventor： Tsu Ching Yang , Feng-Cheng Yang , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Hung-Chang Sun , Chen-Jun Wu , Chung-Te Lin
Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.
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公开(公告)号：US20230262985A1
公开(公告)日：2023-08-17
申请号：US18308031
申请日：2023-04-27
Inventor： Chen-Jun Wu , Yu-Wei Jiang , Sheng-Chih Lai
IPC: H10B43/35 , H01L23/522 , H10B41/27 , H10B41/35 , H10B43/27
CPC classification number: H10B43/35 , H01L23/5226 , H10B41/27 , H10B41/35 , H10B43/27
Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.
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公开(公告)号：US12048164B2
公开(公告)日：2024-07-23
申请号：US18151483
申请日：2023-01-09
Inventor： Wen-Ling Lu , Chen-Jun Wu , Ya-Yun Cheng , Sheng-Chih Lai , Yi-Ching Liu , Yu-Ming Lin , Feng-Cheng Yang , Chung-Te Lin
CPC classification number: H10B51/30 , G11C11/223 , G11C11/2275 , H10B51/20
Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
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Patent Agency Ranking
公开(公告)号：US20240090230A1
公开(公告)日：2024-03-14
申请号：US18151483
申请日：2023-01-09
Inventor： Wen-Ling Lu , Chen-Jun Wu , Ya-Yun Cheng , Sheng-Chih Lai , Yi-Ching Liu , Yu-Ming Lin , Feng-Cheng Yang , Chung-Te Lin
CPC classification number: H10B51/30 , G11C11/223 , G11C11/2275 , H10B51/20
Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
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公开(公告)号：US20250069648A1
公开(公告)日：2025-02-27
申请号：US18947545
申请日：2024-11-14
Inventor： Chen-Jun Wu , Yun-Feng Kao , Sheng-Chih Lai , Katherine H. Chiang , Chung-Te Lin
IPC: G11C11/4096
Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
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公开(公告)号：US20240038294A1
公开(公告)日：2024-02-01
申请号：US17878200
申请日：2022-08-01
Inventor： Chen-Jun Wu , Yun-Feng Kao , Sheng-Chih Lai , Katherine H. Chiang , Chung-Te Lin
IPC: G11C11/4096
CPC classification number: G11C11/4096
Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
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公开(公告)号：US20230328980A1
公开(公告)日：2023-10-12
申请号：US18336252
申请日：2023-06-16
Inventor： Tsu Ching Yang , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Hung-Chang Sun , Chen-Jun Wu , Feng-Cheng Yang , Chung-Te Lin
Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.
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公开(公告)号：US12176022B2
公开(公告)日：2024-12-24
申请号：US17878200
申请日：2022-08-01
Inventor： Chen-Jun Wu , Yun-Feng Kao , Sheng-Chih Lai , Katherine H. Chiang , Chung-Te Lin
IPC: G11C11/4096
Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
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