公开(公告)号：US08865481B2

公开(公告)日：2014-10-21

申请号：US14172208

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L29/82 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US11710733B2

公开(公告)日：2023-07-25

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Bharani Chava ,  Foua Vang ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: H01L27/02 ,  H03K19/0185 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H03K19/018557

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P.

公开(公告)号：US10460817B2

公开(公告)日：2019-10-29

申请号：US15817474

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Wei-Chuan Chen

IPC: G11C7/00 ,  G11C16/34 ,  G11C11/56 ,  G11C14/00 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L45/00 ,  G06N3/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08 ,  G11C7/18 ,  G11C8/14 ,  H03K19/177

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

公开(公告)号：US20190305971A1

公开(公告)日：2019-10-03

申请号：US15944089

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Seung Hyuk Kang

IPC: H04L9/32 ,  G11C11/419 ,  G11C7/12

Abstract: Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells enhanced by stress for increased PUF output reproducibility. Stress voltage applied to SRAM bit cells enhances their skew so that the SRAM bit cells output their preferred initial state in subsequent PUF read operations regardless of process variation and other external environmental variations, such as temperature. The application of stress voltage on the SRAM bit cells in a PUF memory array takes advantage of the recognition of aging effect in transistors, where turning transistors on and off over time can increase threshold voltage resulting in lower drive current. Stress voltage can be applied to the SRAM bit cells to bias their threshold voltage to simulate this aging effect to enhance mismatch between transistors in the SRAM bit cell to more fully skew the SRAM bit cells for increased PUF output reproducibility with less susceptible to noise.

公开(公告)号：US20190304527A1

公开(公告)日：2019-10-03

申请号：US15939923

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Sungryul Kim ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H04L9/32 ,  H01L43/08 ,  H01L27/22

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

公开(公告)号：US10431278B2

公开(公告)日：2019-10-01

申请号：US15676957

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C5/14 ,  G11C7/04 ,  G11C29/50 ,  H01L27/22 ,  H01L43/08

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

公开(公告)号：US10319425B1

公开(公告)日：2019-06-11

申请号：US15939514

申请日：2018-03-29

Applicant: QUALCOMM Incorporated ,  Yonsei University, University-Industry Foundation

Inventor： Seong-Ook Jung ,  Byungkyu Song ,  Sungryul Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

Abstract: Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.

公开(公告)号：US10312244B2

公开(公告)日：2019-06-04

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US20180372685A1

公开(公告)日：2018-12-27

申请号：US16057452

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G01N27/74 ,  G01R33/09 ,  B82Y25/00

Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.

公开(公告)号：US10103319B2

公开(公告)日：2018-10-16

申请号：US15458641

申请日：2017-03-14

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Jimmy Kan ,  Xiaochun Zhu ,  Matthias Georg Gottwald ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32

Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.