公开(公告)号：US20130134533A1

公开(公告)日：2013-05-30

申请号：US13683783

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Matthew Nowak ,  Xia Li ,  Seung H. Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：US20170178741A1

公开(公告)日：2017-06-22

申请号：US15450055

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C17/02 ,  G11C11/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

公开(公告)号：US09298946B2

公开(公告)日：2016-03-29

申请号：US14072735

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C17/02 ,  G06F21/70 ,  G06F1/26 ,  G11C11/16 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00

CPC classification number: G06F21/70 ,  G06F1/26 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C17/02 ,  G11C17/14 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆的功能的方法，其包括提供金属 - 绝缘体 - 金属（MIM）器件的阵列，其中MIM器件被配置为表示第一电阻状态或第二电阻状态，并且多个 MIM器件最初处于第一电阻状态。 MIM器件具有大于第一电压且小于第二电压的随机击穿电压，其中击穿电压表示使MIM器件从第一电阻状态转变到第二电阻状态的电压。 该方法还包括向MIM器件施加信号线电压以使MIM器件的一部分随机击穿并从第一电阻状态转变到第二电阻状态，信号线电压大于第一电压并小于 第二电压。

公开(公告)号：US09214624B2

公开(公告)日：2015-12-15

申请号：US13770526

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Wei-Chuan Chen ,  Seung H. Kang

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/15 ,  G11C11/16

CPC classification number: H01L43/10 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract translation: 垂直磁隧道结（MTJ）装置包括沉积在隧道势垒层和参考层之间的隧道磁阻（TMR）增强缓冲层。在TMR增强缓冲层和参考层之间沉积非晶合金间隔物以增强TMR非晶态 合金间隔块阻挡面心立方（fcc）取向钉扎层的模板效应，并且在钉扎层和TMR增强缓冲层之间提供强耦合，以确保完全垂直磁化。

公开(公告)号：US09105310B2

公开(公告)日：2015-08-11

申请号：US13759310

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: G11C11/34 ,  G11C11/40 ,  G11C17/12 ,  G11C5/02 ,  G11C7/00 ,  G11C17/16 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  G11C7/12 ,  G11C11/404

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

Abstract translation: 一种方法包括在包括重叠区域和沟道区域的半导体晶体管结构下产生击穿条件。 通过使半导体晶体管结构的栅极和重叠区域之间的第一电压差超过半导体晶体管结构的击穿电压，同时保持栅极和沟道区域之间的第二电压差小于 击穿电压。

公开(公告)号：US20150071432A1

公开(公告)日：2015-03-12

申请号：US14077093

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David Merrill Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to least one physically unclonable function based on an array of magnetoresistive random-access memory (MRAM) cells. A challenge to the array of MRAM cells may identify some of the cells to be used for the physically unclonable function. Each MRAM cell may include a plurality of magnetic tunnel junctions (MTJs), where the MTJs may exhibit distinct resistances due to manufacturing or fabrication variations. A response to the challenge may be obtained for each cell by using the resistance(s) of one or both of the MTJs for a cell to obtain a value that serves as the response for that cell. The responses for a plurality of cells may be at least partially mapped to provide a unique identifier for the array. The responses generated from the array of cells may serve as a physically unclonable function that may be used to uniquely identify an electronic device.

Abstract translation: 一个特征涉及基于磁阻随机存取存储器（MRAM）单元阵列的至少一个物理上不可克隆的功能。 对MRAM单元阵列的挑战可能会识别要用于物理不可克隆功能的一些单元格。 每个MRAM单元可以包括多个磁隧道结（MTJ），其中MTJ可能由于制造或制造变化而呈现出不同的电阻。 可以通过使用用于单元的MTJ中的一个或两个的电阻来获得用作该单元的响应的值，为每个单元获得对该挑战的响应。 可以至少部分地映射多个小区的响应以提供阵列的唯一标识符。 从单元阵列产生的响应可以用作可以用于唯一地识别电子设备的物理上不可克隆的功能。

公开(公告)号：US20140269031A1

公开(公告)日：2014-09-18

申请号：US13835251

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。

公开(公告)号：US20140254251A1

公开(公告)日：2014-09-11

申请号：US13787938

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Kangho Lee ,  Wah Nam Hsu ,  Xiao Lu ,  Seung H. Kang

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C7/04 ,  G11C11/16 ,  G11C29/00 ,  G11C29/56016

Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.

Abstract translation: 在特定实施例中，一种方法包括在施加磁场的同时控制室内的温度。 包括存储器阵列的装置位于腔室中。 该方法包括在存储器阵列中施加磁场并在目标温度下将磁场施加到存储器阵列期间测试存储器阵列。

公开(公告)号：US20140015080A1

公开(公告)日：2014-01-16

申请号：US14036409

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Seung H. Kang ,  Xia Li ,  Shiqun Gu ,  Kangho Lee ,  Xiaochun Zhu

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

Abstract translation: 用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）装置包括与至少一个控制装置通信的第一导电互连和通过形成在电介质钝化屏障中的通孔连接到第一导电互连的第一电极，其使用 第一个面具。 该装置具有用于存储耦合到第一电极的数据的MTJ堆叠。 MTJ堆叠的一部分具有基于第二掩模的横向尺寸。 由第二掩模限定的部分在接触通孔之上。 第二电极耦合到MTJ堆叠并且还具有由第二掩模限定的横向尺寸。 第一电极和MTJ堆叠的一部分由第三掩模限定。 第二导电互连件耦合到第二电极和至少一个其它控制装置。

公开(公告)号：US20130314980A1

公开(公告)日：2013-11-28

申请号：US13953780

申请日：2013-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Seung H. Kang

IPC: G11C11/16

CPC classification number: G11C11/1653 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

Abstract translation: 旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。 具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。 在写入操作期间可以应用来自其中一个电源的电压。