公开(公告)号：US20200020582A1

公开(公告)日：2020-01-16

申请号：US16058095

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/768 ,  H01L21/311

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and a semiconductor element is formed on the third fin structure.

公开(公告)号：US20190067188A1

公开(公告)日：2019-02-28

申请号：US16058290

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Shih Wei BIH ,  Yen-Yu CHEN

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

公开(公告)号：US20160230275A1

公开(公告)日：2016-08-11

申请号：US15099687

申请日：2016-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Chien-Hao TSENG ,  Yen-Yu CHEN ,  Ching-Chia WU ,  Chang-Sheng LEE ,  Wei ZHANG

IPC: C23C16/44 ,  H01L29/51 ,  H01L21/28 ,  C23C16/448 ,  C23C16/455

CPC classification number: C23C16/4402 ,  C23C16/4481 ,  C23C16/4485 ,  C23C16/45544 ,  C23C16/45553 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28185 ,  H01L29/517

Abstract: A method for fabricating a semiconductor structure and a solid precursor delivery system for a semiconductor fabrication is provided, the method including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film.

Abstract translation: 提供一种制造用于半导体制造的半导体结构和固体前体输送系统的方法，所述方法包括：提供具有第一平均粒度的固体前体; 将有机溶剂中的固体前体溶解成中间体; 使中间体重结晶形成固体颗粒，其中固体颗粒具有大于第一平均粒度的第二平均粒径; 蒸发固体颗粒以形成成膜气体; 并将成膜气体沉积在基板上以形成电阻膜。

公开(公告)号：US20250157919A1

公开(公告)日：2025-05-15

申请号：US19024920

申请日：2025-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu CHEN ,  Chung-Liang CHENG

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US20250098241A1

公开(公告)日：2025-03-20

申请号：US18962886

申请日：2024-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

公开(公告)号：US20240387676A1

公开(公告)日：2024-11-21

申请号：US18785512

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

公开(公告)号：US20240381621A1

公开(公告)日：2024-11-14

申请号：US18783146

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94

Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

公开(公告)号：US20230377993A1

公开(公告)日：2023-11-23

申请号：US18227744

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/32139 ,  H01L21/32133 ,  H01L21/28556 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/0847 ,  H01L27/0924

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

公开(公告)号：US20230352553A1

公开(公告)日：2023-11-02

申请号：US18347480

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/4908 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32135 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L27/092 ,  G05B13/0265

Abstract: A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

公开(公告)号：US20230296523A1

公开(公告)日：2023-09-21

申请号：US18324021

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: G01N21/64 ,  G01N21/95 ,  G06F30/27 ,  C23C14/54 ,  G06N3/08

CPC classification number: G01N21/6489 ,  G01N21/9501 ,  G06F30/27 ,  C23C14/548 ,  G06N3/08 ,  B82Y30/00

Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.