公开(公告)号：US20190267292A1

公开(公告)日：2019-08-29

申请号：US16408877

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width.

公开(公告)号：US10290548B2

公开(公告)日：2019-05-14

申请号：US15692188

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.

公开(公告)号：US20190109204A1

公开(公告)日：2019-04-11

申请号：US16201523

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092

Abstract: A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.

公开(公告)号：US10164042B2

公开(公告)日：2018-12-25

申请号：US15418995

申请日：2017-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia Yeo ,  Hung-Li Chiang ,  Jyh-Cherng Sheu ,  Sung-Li Wang ,  I-Sheng Chen ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/45 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US10002969B2

公开(公告)日：2018-06-19

申请号：US15407839

申请日：2017-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/24 ,  H01L29/267 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

公开(公告)号：US20250151337A1

公开(公告)日：2025-05-08

申请号：US19014431

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H10D30/67 ,  H10D30/01 ,  H10D62/10 ,  H10D64/01 ,  H10D84/85

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US12211895B2

公开(公告)日：2025-01-28

申请号：US17202237

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

公开(公告)号：US11984476B2

公开(公告)日：2024-05-14

申请号：US17875565

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/76 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0649 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

公开(公告)号：US11289384B2

公开(公告)日：2022-03-29

申请号：US17114347

申请日：2020-12-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Lei-Chun Chou

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

公开(公告)号：US11177179B2

公开(公告)日：2021-11-16

申请号：US16914747

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  G03F1/38 ,  H01L21/308 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/78 ,  H01L29/775 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.