公开(公告)号：US12237425B2

公开(公告)日：2025-02-25

申请号：US18332938

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H Diaz

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US11715802B2

公开(公告)日：2023-08-01

申请号：US17181315

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H Diaz

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L27/092

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US11245005B2

公开(公告)日：2022-02-08

申请号：US16868625

申请日：2020-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon-Jhy Liaw ,  Chao-Ching Cheng ,  Hung-Li Chiang ,  Shih-Syuan Huang ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Sai-Hooi Yeong

IPC: H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.

公开(公告)号：US11239075B2

公开(公告)日：2022-02-01

申请号：US16728393

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Wu ,  I-Sheng Chen

IPC: H01L31/072 ,  H01L31/109 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04

Abstract: A structure includes a substrate having a first semiconductor material. The substrate has a recess. A bottom portion of the recess has a first sidewall and a second sidewall. The first sidewall intersects the second sidewall. The structure further includes an isolation feature surrounding the recess and a second semiconductor material disposed in the recess and in contact with the first semiconductor material. The second semiconductor material has lattice mismatch to the first semiconductor material.

公开(公告)号：US11043570B2

公开(公告)日：2021-06-22

申请号：US16814154

申请日：2020-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia Yeo ,  Sung-Li Wang ,  Chi On Chui ,  Jyh-Cherng Sheu ,  Hung-Li Chiang ,  I-Sheng Chen

IPC: H01L21/8234 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20210175367A1

公开(公告)日：2021-06-10

申请号：US17181315

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10861750B2

公开(公告)日：2020-12-08

申请号：US16281679

申请日：2019-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  I-Sheng Chen ,  Lei-Chun Chou

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

公开(公告)号：US10516056B2

公开(公告)日：2019-12-24

申请号：US15986426

申请日：2018-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/786 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/08

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

公开(公告)号：US20190103472A1

公开(公告)日：2019-04-04

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/51 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20180350590A1

公开(公告)日：2018-12-06

申请号：US15704992

申请日：2017-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Wu ,  I-Sheng Chen

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A structure includes a substrate including a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls.