公开(公告)号：US20190237557A1

公开(公告)日：2019-08-01

申请号：US16383542

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han LIN ,  Shih-Chang TSAI ,  Wen-Shuo HSIEH ,  Te-Yung LIU

IPC: H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L29/786 ,  H01L51/52 ,  H01L21/02 ,  H01L27/12 ,  H01L27/088 ,  H01L21/84

CPC classification number: H01L29/4908 ,  H01L21/02104 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/04 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7869 ,  H01L51/5203

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

公开(公告)号：US20190122933A1

公开(公告)日：2019-04-25

申请号：US16222621

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.

公开(公告)号：US20180277544A1

公开(公告)日：2018-09-27

申请号：US15990807

申请日：2018-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/3215 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/28114 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7851

Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

公开(公告)号：US20170222055A1

公开(公告)日：2017-08-03

申请号：US15089380

申请日：2016-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.

公开(公告)号：US20170194199A1

公开(公告)日：2017-07-06

申请号：US14984568

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76831 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528

Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure, a conductive structure and an anti-adhesion layer. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The via opening has a sidewall. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. The anti-adhesion layer is present between the sidewall of the via opening of the dielectric structure and the conductive structure.

公开(公告)号：US20170194149A1

公开(公告)日：2017-07-06

申请号：US14984555

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Po-Chi WU ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L21/225 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/2253 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

公开(公告)号：US20170178975A1

公开(公告)日：2017-06-22

申请号：US15016144

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/7848

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.

公开(公告)号：US20170110454A1

公开(公告)日：2017-04-20

申请号：US15392693

申请日：2016-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height Hb, which is less than ¾ of a height Ha of the separation plug.

公开(公告)号：US20160343862A1

公开(公告)日：2016-11-24

申请号：US14813799

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7856 ,  H01L21/32133 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的鳍结构。 半导体器件结构还包括覆盖鳍结构的一部分的栅极堆叠。 栅堆叠包括与鳍结构相邻的第一部分和第二部分，并且第一部分比第二部分宽。

公开(公告)号：US20160240650A1

公开(公告)日：2016-08-18

申请号：US14621805

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract translation: 提供半导体结构及其形成方法。 该半导体结构包括在基板上形成的基板和翅片结构。 半导体结构还包括形成在翅片结构周围的隔离结构和横跨翅片结构形成的栅极结构。 此外，栅极结构包括形成在鳍状结构上的第一部分和形成在隔离结构上的第二部分，并且栅极结构的第二部分包括延伸到隔离结构中的延伸部分。