公开(公告)号：US09330770B2

公开(公告)日：2016-05-03

申请号：US14590665

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09202570B2

公开(公告)日：2015-12-01

申请号：US14142158

申请日：2013-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Wonseok Cho

IPC: H01L29/40 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

Abstract translation: 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

公开(公告)号：US09190533B2

公开(公告)日：2015-11-17

申请号：US14614908

申请日：2015-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun Son ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/115

CPC classification number: H01L21/28 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/7889

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

公开(公告)号：US09117923B2

公开(公告)日：2015-08-25

申请号：US13830208

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmin Hwang ,  Wonseok Cho ,  Jinsoo Lim

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.

Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。

公开(公告)号：US09012320B2

公开(公告)日：2015-04-21

申请号：US14258436

申请日：2014-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee ,  Kil-Su Jeong ,  Hansoo Kim ,  Youngwoo Park

IPC: H01L27/115

CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract translation: 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

公开(公告)号：US08969162B2

公开(公告)日：2015-03-03

申请号：US13933772

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US08824209B2

公开(公告)日：2014-09-02

申请号：US13836212

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。

公开(公告)号：US08637920B2

公开(公告)日：2014-01-28

申请号：US13684857

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract translation: 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20130082316A1

公开(公告)日：2013-04-04

申请号：US13684645

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun SON ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

IPC: H01L29/788

CPC classification number: H01L21/28 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/7889

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.