公开(公告)号：US20200212063A1

公开(公告)日：2020-07-02

申请号：US16811171

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkeun SON ,  Yoocheol SHIN ,  Changhyun LEE ,  Hyunjung KIM ,  Chung-Il HYUN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11556

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

公开(公告)号：US20180219022A1

公开(公告)日：2018-08-02

申请号：US15935498

申请日：2018-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun SON ,  Yoocheol SHIN ,  Changhyun LEE ,  Hyunjung KIM ,  Chung-II HYUN

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/40117

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

公开(公告)号：US20140065810A1

公开(公告)日：2014-03-06

申请号：US14074817

申请日：2013-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkeun SON ,  Changhyun LEE ,  Jaegoo LEE ,  Kwang Soo SEOL ,  Byungkwan YOU

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

Abstract: A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

Abstract translation: 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。

公开(公告)号：US20130082316A1

公开(公告)日：2013-04-04

申请号：US13684645

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun SON ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

IPC: H01L29/788

CPC classification number: H01L21/28 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/7889

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

公开(公告)号：US20190341401A1

公开(公告)日：2019-11-07

申请号：US16516793

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungkeun SON ,  Yoocheol SHIN ,  Changhyun LEE ,  Hyunjung KIM ,  Chung-lI HYUN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.