公开(公告)号：US20200020688A1

公开(公告)日：2020-01-16

申请号：US16034703

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L27/02

Abstract: Integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) for reduced gate layout parasitic capacitance, and related methods, are disclosed. In exemplary aspects, the gate topography (e.g., height) of a gate in a circuit cell used to form gates for devices formed therein to form an integrated circuit is varied between an active gate and a field gate(s) of the gate. In this manner, the overall volume of material in the gate can be reduced due to the reduction in volume of the field gate(s) to reduce gate layout parasitic capacitance. Reducing gate layout parasitic capacitance in a circuit cell can reduce the overall parasitic capacitance of an integrated circuit formed from the circuit cell to achieve the desired integrated circuit delay performance.

公开(公告)号：US10283526B2

公开(公告)日：2019-05-07

申请号：US15386501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu

IPC: H01L27/10 ,  H01L27/118 ,  H01L21/8234 ,  H01L23/50 ,  H01L23/538 ,  H01L23/528 ,  H01L27/02

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

公开(公告)号：US20180175060A1

公开(公告)日：2018-06-21

申请号：US15386501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu

IPC: H01L27/118 ,  H01L21/8234 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

公开(公告)号：US20180033729A1

公开(公告)日：2018-02-01

申请号：US15634039

申请日：2017-06-27

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L23/5283 ,  G06F17/5072 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53257 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

公开(公告)号：US09728718B2

公开(公告)日：2017-08-08

申请号：US15389322

申请日：2016-12-22

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Matthias Georg Gottwald ,  Mustafa Badaroglu ,  Jimmy Kan ,  Kangho Lee ,  Yu Lu ,  Chando Park

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

公开(公告)号：US20170140986A1

公开(公告)日：2017-05-18

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US20160293485A1

公开(公告)日：2016-10-06

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract translation: 翅片型半导体器件包括栅极结构和源极/漏极结构。 翅片型半导体器件还包括耦合到栅极结构的栅极硬掩模结构。 门硬掩模结构包括第一材料。 翅片型半导体器件还包括耦合到源极/漏极结构的源极/漏极硬掩模结构。 源极/漏极硬掩模结构包括第二材料。

公开(公告)号：US20160049487A1

公开(公告)日：2016-02-18

申请号：US14670268

申请日：2015-03-26

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/785

Abstract: A device includes a first structure and a second structure. The second structure is separated from the first structure by a cavity. The device further includes a seal material, an etch stop material defining an etched region, and a self-aligned contact (SAC). The seal material is configured to seal the cavity, and the SAC is formed within the etched region. The SAC adjoins the seal material, the etch stop material, or a combination thereof.

Abstract translation: 一种装置包括第一结构和第二结构。 第二结构通过空腔与第一结构分离。 该装置还包括密封材料，限定蚀刻区域的蚀刻停止材料和自对准接触（SAC）。 密封材料构造成密封空腔，并且在蚀刻区域内形成SAC。 SAC邻接密封材料，蚀刻停止材料或其组合。