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    Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system
    43.
    发明申请
    Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system 失效
    具有改进的阻抗控制电路，电气组装和信息处理系统的电路化衬底的方法

    公开(公告)号：US20070284140A1

    公开(公告)日：2007-12-13

    申请号：US11889668

    申请日：2007-08-15

    Applicant: Charles Danoski ,  Irving Memis ,  Steven Rosser

    Inventor： Charles Danoski ,  Irving Memis ,  Steven Rosser

    IPC: H01R12/04 ,  H05K3/00 ,  H05K3/34 ,  H05K5/00

    CPC classification number: H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

    Abstract: A method of making a circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The produced substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. An electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

    Abstract translation: 制造电路化衬底的方法被设计为基本上消除信号通过衬底电路的信号线时的阻抗中断。 所生产的衬底包括具有多个导体的第一导电层，电组件可在其上定位并电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了利用该基板的电组件和信息处理系统（例如，计算机）。

    High performance chip carrier substrate
    44.
    发明授权
    High performance chip carrier substrate 有权
    高性能芯片载体基板

    公开(公告)号：US07214886B2

    公开(公告)日：2007-05-08

    申请号：US10722226

    申请日：2003-11-25

    Applicant: Jean Audet ,  Irving Memis

    Inventor： Jean Audet ,  Irving Memis

    IPC: H05K1/16

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

    Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

    Abstract translation: 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出外，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

    High density microvia substrate with high wireability
    46.
    发明授权
    High density microvia substrate with high wireability 失效
    具有高线性的高密度微孔基材

    公开(公告)号：US06919635B2

    公开(公告)日：2005-07-19

    申请号：US10701311

    申请日：2003-11-04

    Applicant: Kazushige Kawasaki ,  Irving Memis

    Inventor： Kazushige Kawasaki ,  Irving Memis

    IPC: H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

    CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/029 ,  H05K2201/09609 ,  H05K2201/09627

    Abstract: The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or regions having a width approximately the diameter of the holes and running along orthogonal columns and rows of holes, parallel to the direction of fibers, define regions of fibers that can possibly cause shorting between holes. Rotating a conventional X-Y grid pattern of equidistant holes so as to position, for example, alternate holes in one direction between the elongated strip zones running in the opposite direction significantly increases the distance between holes along the elongated strip zones running in each direction. The holes are positioned between elongated strip zones with sufficient clearance to compensate for variations in the linear path of fibers.

    Abstract translation: 基于玻璃纤维的芯片载体中的电镀通孔的密度通过偏移孔增加到相邻孔的纤维将不连接的位置。 宽度大约为孔的宽度的区域或区域平行于纤维方向的正交列和孔排沿着孔的直径延伸，限定了可能导致孔之间短路的纤维区域。 旋转等距孔的常规X-Y网格图案，以便例如在沿相反方向运行的细长条带之间的一个方向上的交替孔定位显着地增加沿着沿每个方向运行的细长条带的孔之间的距离。 孔位于具有足够间隙的细长带区之间以补偿纤维线性路径的变化。

    High performance chip carrier substrate
    47.
    发明申请
    High performance chip carrier substrate 有权
    高性能芯片载体基板

    公开(公告)号：US20050109535A1

    公开(公告)日：2005-05-26

    申请号：US10722226

    申请日：2003-11-25

    Applicant: Jean Audet ,  Irving Memis

    Inventor： Jean Audet ,  Irving Memis

    IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/30 ,  H01L23/48

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

    Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

    Abstract translation: 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出外，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby
    50.
    发明授权
    Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby 有权
    在平面化薄膜电介质和由此制造的电路上设计和制造细线电路的方法

    公开(公告)号：US06290860B1

    公开(公告)日：2001-09-18

    申请号：US09283679

    申请日：1999-04-01

    Applicant: Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    Inventor： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    IPC: H01B1300

    CPC classification number: H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

    Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

    Abstract translation: 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

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