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    High performance chip carrier substrate
    1.
    发明授权
    High performance chip carrier substrate 失效
    高性能芯片载体基板

    公开(公告)号：US07454833B2

    公开(公告)日：2008-11-25

    申请号：US11651631

    申请日：2007-01-09

    Applicant: Jean Audet ,  Irving Memis

    Inventor： Jean Audet ,  Irving Memis

    IPC: H05K3/00 ,  H05K3/10

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

    Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

    Abstract translation: 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

    SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS
    2.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS 有权
    具有非对准活性VIAS的半导体封装

    公开(公告)号：US20080054482A1

    公开(公告)日：2008-03-06

    申请号：US11469950

    申请日：2006-09-05

    Applicant: Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

    Inventor： Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

    IPC: H01L23/48

    CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

    Abstract translation: 公开了一种半导体封装，其包括通过绝缘体与相邻的第二捕获垫隔离的第一捕获垫; 将第一捕获垫连接到第二捕获垫的第一多个电活动通孔; 通过绝缘体与第二捕获垫隔离的第三捕获垫; 以及将第二捕获垫连接到第三捕获垫的第二多个电活动通孔。 第一多个有源通孔的每个通孔与第二多个有源通孔的每个通孔不对齐。 当将剪切力施加到与其一起使用的球栅阵列同时最小化电信号的劣化时，该结构提供通孔上的应变减小。

    Electronic package having high density signal wires with low resistance
    6.
    发明授权
    Electronic package having high density signal wires with low resistance 有权
    电子封装具有低电阻的高密度信号线

    公开(公告)号：US06762367B2

    公开(公告)日：2004-07-13

    申请号：US10246147

    申请日：2002-09-17

    Applicant: Jean Audet ,  Timothy W. Budell ,  Patrick H. Buffet

    Inventor： Jean Audet ,  Timothy W. Budell ,  Patrick H. Buffet

    IPC: H05K103

    CPC classification number: H05K1/0265 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/0352 ,  H05K2201/09627 ,  H05K2201/09736 ,  H05K2201/10674 ,  H01L2224/0401

    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.

    Abstract translation: 在本发明中，电子封装组件包括位于衬底上的集成电路。 衬底具有基本水平的层，包括垂直厚度和电阻的水平信号线。 在优选实施例中，信号线的第一和第二垂直厚度从衬底的顶部到底部交替，使得具有较大垂直厚度的信号线具有比信号线通常具有的更低的电阻。 多个基本垂直的导电通孔穿过水平层，使得垂直导电通孔连接到集成电路并与至少一个水平信号线连接。 位于基板下方的电路板包括用于连接并终止垂直导电通孔的连接构件。

    Method and apparatus for continuous cleaning of substrate surfaces using ozone
    8.
    发明授权
    Method and apparatus for continuous cleaning of substrate surfaces using ozone 失效
    使用臭氧连续清洗基材表面的方法和设备

    公开(公告)号：US06461443B1

    公开(公告)日：2002-10-08

    申请号：US09574889

    申请日：2000-05-19

    Applicant: Jean Audet ,  Mario Leboeuf ,  Isabelle Tremblay ,  Herbert P. R. Wossidlo

    Inventor： Jean Audet ,  Mario Leboeuf ,  Isabelle Tremblay ,  Herbert P. R. Wossidlo

    IPC: F23J100

    CPC classification number: H01L21/67109 ,  H01L21/67028

    Abstract: The present invention provides new and improved methods and apparatus for removing contamination from surfaces of substrates. Existing techniques include plasma ashing, glow discharge or UV/ozone processes. The present invention includes cleaning the substrate surfaces by transporting the substrates to be cleaned through a first zone where the substrates are heated preferably in a nitrogen atmosphere and then to a second zone where the substrates are surrounded by an atmosphere of ozone. The organic contamination is thereby vaporized into vapor products including CO, CO2 and H2O.

    Abstract translation: 本发明提供了用于从衬底表面去除污染物的新的和改进的方法和装置。 现有技术包括等离子体灰化，辉光放电或UV /臭氧工艺。 本发明包括通过第一区域输送要清洗的基材来清洗基板表面，其中基板最好在氮气气氛中被加热，然后到第二区域，其中基板被臭氧气氛包围。 有机污染物因此蒸发成蒸气产物，包括CO，CO2和H2O。

    Tool holding apparatus used on lathes for cutting various curved shapes
    9.
    发明授权
    Tool holding apparatus used on lathes for cutting various curved shapes 失效
    用于切割各种曲线形状的刀具的工具保持装置

    公开(公告)号：US3566722A

    公开(公告)日：1971-03-02

    申请号：US3566722D

    申请日：1968-12-03

    Applicant: JEAN AUDET

    Inventor： AUDET JEAN

    IPC: B23B5/40 ,  B23B29/06 ,  B23B29/12

    CPC classification number: B23B29/12 ,  B23B5/40 ,  B23B29/06 ,  Y10T82/148

    Abstract: THIS INVENTION RELATES TO A TOOL HOLDING APPARATUS USED ON LATHES FOR CUTTING VARIOUS CURVED SHAPES. THE TOOL HOLDING APPARATUS INCLUDES A CASING MOUNTED ON THE CARRIAGE OF A LATHE AND ENCLOSING A HYDRAULIC MOTOR COUPLED TO A SHAFT. THE SHAFT OF THE MOTOR IS COUPLED TO A ADJUSTABLE RADIUS BAR WHICH IS LOCATED OUTSIDE THE CASING AND ADAPTED TO OSCILLATE A PREDETERMINED NUMBER OF DEGREES DEPENDING ON THE AMOUNT OF ROTATION OF THE MOTOR IN BOTH DIRECTIONS. THE SHAFT OF THE MOTOR IS ALSO COUPLED TO A SWIVEL MEMBER LOCATED OUTSIDE THE CASING AND USED TO EXECUTE VARIOUS CURVED SHAPED IN THE INTERIOR OF A WORKPIECE.

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