公开(公告)号：US20170084609A1

公开(公告)日：2017-03-23

申请号：US15369951

申请日：2016-12-06

申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

发明人： Trudy Benjamin

IPC分类号： H01L27/06 ,  B41J2/14 ,  H01L29/10

CPC分类号： H01L27/0629 ,  B41J2/1433 ,  B41J2002/14491 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1033 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/783

摘要： In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

公开(公告)号：US20160351699A1

公开(公告)日：2016-12-01

申请号：US14721648

申请日：2015-05-26

申请人： NXP B.V.

发明人： Priscilla Boos ,  Arjan Mels

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/783 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7823

摘要： A field-effect transistor (FET) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region. A plurality of body dropdowns are located in the gate region and are spaced along a width of the gate region. Each of the body dropdowns are configured and arranged to provide an electrical contact to the body for biasing purposes.

摘要翻译： 场效应晶体管（FET）包括第一漏极，第二漏极，主体和栅极区域。 栅极区域具有长度，并且被配置和布置成响应于栅极电压而产生在主体中，在第一和第二漏极之间以及沿着栅极区域的长度的沟道。 多个主体下拉位于栅极区域中并且沿着栅极区域的宽度间隔开。 每个身体下拉装置被构造和布置成为身体提供用于偏压目的的电接触。

公开(公告)号：US09449678B2

公开(公告)日：2016-09-20

申请号：US14752514

申请日：2015-06-26

申请人： Renesas Electronics Corporation

发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC分类号： H01L29/76 ,  H01L27/11 ,  G11C11/412 ,  G11C11/417

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

摘要： A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

摘要翻译： 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

公开(公告)号：US09178034B2

公开(公告)日：2015-11-03

申请号：US14206085

申请日：2014-03-12

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Masahiro Fukuda ,  Eiji Yoshida ,  Yosuke Shimamune

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/12

CPC分类号： H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/783 ,  H01L29/7848

摘要： A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

摘要翻译： 一种方法包括：除硅衬底部分之外，蚀刻硅衬底，在其上形成沟道区以在硅衬底部分的第一侧和第二侧分别形成第一和第二沟槽; 通过外延生长具有对硅蚀刻选择性的半导体层和另外的硅层来填充第一和第二沟槽; 通过选择性蚀刻工艺去除半导体层选择性，以在衬底部分的第一侧和第二侧分别在硅层下形成空隙; 至少部分地用掩埋绝缘膜掩埋空隙; 在所述硅衬底部分上形成栅极绝缘膜和栅电极; 以及在所述硅衬底部分的第一侧的所述硅层中形成源极区域以及在所述硅衬底部分的第二侧处形成漏极区域。

公开(公告)号：US09165926B2

公开(公告)日：2015-10-20

申请号：US14044665

申请日：2013-10-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jam-Wem Lee

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L27/06 ,  H01L27/12

CPC分类号： H01L29/66651 ,  H01L21/187 ,  H01L21/304 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/783 ,  H01L29/78615 ,  H01L2224/11

摘要： A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.

摘要翻译： 芯片包括半导体衬底，半导体衬底中的阱区和形成在半导体衬底的前侧的动态阈值金属氧化物半导体（DTMOS）晶体管。 DTMOS晶体管包括栅电极和与栅电极相邻的源/漏区。 源极/漏极区域设置在阱区域中。 阱拾取区域在阱区中，阱拾取区域位于半导体衬底的背面。 阱拾取区域电连接到栅电极。

公开(公告)号：US20150123206A1

公开(公告)日：2015-05-07

申请号：US14450445

申请日：2014-08-04

申请人： MediaTek Inc.

发明人： Cheng-Chou HUNG ,  Tung-Hsing LEE ,  Bernard Mark TENBROEK ,  Rong-Tang CHEN

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/783 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78657

摘要： The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.

摘要翻译： 本发明提供一种体接触金属氧化物半导体场效应晶体管（MOSFET）器件。 体接触MOSFET器件包括衬底。 有源区设置在基板上。 栅极条沿着设置在有源区域的第一部分上的第一方向延伸。 源极掺杂区域和漏极掺杂区域设置在与栅极条的相对侧相邻的有源区域的第二部分和第三部分上。 栅极条的相对侧沿第一方向延伸。 体接触掺杂区域设置在有源区域的第四部分上。 体接触掺杂区域与有源区域的第五部分与栅极条分离。 第五部分不被任何硅化物特征覆盖。

公开(公告)号：US20140339627A1

公开(公告)日：2014-11-20

申请号：US14449570

申请日：2014-08-01

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio MASUOKA ,  Hiroki NAKAMURA

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/783

摘要： A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer.

摘要翻译： 半导体器件在柱状硅层的上部包括柱状硅层和第一导电型扩散层。 具有绝缘膜和多晶硅层叠结构的侧壁位于柱状硅层的上侧壁上。 侧壁的多晶硅的顶部电连接到第一导电型扩散层的顶部并且具有与扩散层相同的导电性。

公开(公告)号：US08525238B2

公开(公告)日：2013-09-03

申请号：US13198773

申请日：2011-08-05

申请人： Eiji Yoshida

发明人： Eiji Yoshida

IPC分类号： H01L29/76

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/783

摘要： A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.

摘要翻译： 半导体器件制造方法包括：形成包括第一区域的半导体区域，与第一区域连接并且具有比第一区域的宽度小的第二区域，以及与第二区域连接并且具有较小的宽度的第三区域 比第二个地区; 形成包括与所述第三区域交叉的第一部分的栅电极和从所述第一部分延伸穿过所述第一区域的第二部分; 在所述栅电极上形成侧壁绝缘膜以覆盖所述第二区域的一部分，同时暴露所述第二区域的剩余部分; 将第二导电型杂质注入第一区域和第二区域的剩余部分; 进行热处理; 去除所述侧壁绝缘膜的一部分，并且在所述第一区域和所述第二区域的剩余部分上形成硅化物层。

公开(公告)号：US20100034000A1

公开(公告)日：2010-02-11

申请号：US12497210

申请日：2009-07-02

申请人： Marc Battista ,  Hervé Chalopin ,  Hérve Barthelemy

发明人： Marc Battista ,  Hervé Chalopin ,  Hérve Barthelemy

IPC分类号： H02M7/217

CPC分类号： H01L27/0811 ,  H01L27/0727 ,  H01L29/783 ,  H01L29/861 ,  H02M3/07

摘要： An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal.

摘要翻译： 一种包括半导体层的集成电路; 以及MOS晶体管，包括第一和第二电源端子以及与半导体层绝缘的体积，第一电源端子旨在接收振荡信号，晶体管栅极和体积连接到第一电力端子。

公开(公告)号：US20050121699A1

公开(公告)日：2005-06-09

申请号：US10728750

申请日：2003-12-08

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

IPC分类号： H01L27/08 ,  H01L21/8238 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/745 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/783

摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.

摘要翻译： 提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开 根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。 避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 晶体管配置可以与可以互补对的n型和p型晶体管一起使用。