公开(公告)号：US09570437B2

公开(公告)日：2017-02-14

申请号：US14279605

申请日：2014-05-16

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Rob van Dalen ,  Erik Spaan

IPC: H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L21/84 ,  H01L29/73 ,  H01L27/12 ,  H01L29/786 ,  H01L29/861 ,  H01L29/40 ,  H01L21/8249 ,  H01L29/739 ,  H01L29/74

CPC classification number: H01L27/0623 ,  H01L21/7621 ,  H01L21/76221 ,  H01L21/76227 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7302 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78624 ,  H01L29/861

Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract translation: 公开了一种半导体管芯，其包括在衬底的上主表面上的横向半导体器件，所述集成电路包括在衬底上的硅层，在硅层中的凹陷，在凹槽内的LOCOS氧化硅层，并且具有生长 所述上表面与所述硅层的未凹陷部分的表面共面，其中所述凹槽下方的所述硅层具有不均匀的横向掺杂分布，并且包括在所述侧向半导体器件的漂移区域中。 还公开了制造这种裸片的方法，以及集成电路和驱动器电路。

公开(公告)号：US20150194421A1

公开(公告)日：2015-07-09

申请号：US14279605

申请日：2014-05-16

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Rob van Dalen ,  Erik Spaan

IPC: H01L27/06 ,  H01L29/40 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/0623 ,  H01L21/7621 ,  H01L21/76221 ,  H01L21/76227 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7302 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78624 ,  H01L29/861

Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract translation: 公开了一种半导体管芯，其包括在衬底的上主表面上的侧向半导体器件，该集成电路包括衬底上的硅层，在硅层中的凹陷，在凹槽内的一层LOCOS氧化硅，并且具有生长 与硅层的未凹陷部分的表面共面的上表面，其中凹陷下方的硅层具有不均匀的横向掺杂分布，并且包括在横向半导体器件的漂移区域中。 还公开了制造这种裸片的方法，集成电路和驱动电路也是如此。

公开(公告)号：US20160351699A1

公开(公告)日：2016-12-01

申请号：US14721648

申请日：2015-05-26

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Arjan Mels

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/783 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7823

Abstract: A field-effect transistor (FET) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region. A plurality of body dropdowns are located in the gate region and are spaced along a width of the gate region. Each of the body dropdowns are configured and arranged to provide an electrical contact to the body for biasing purposes.

Abstract translation: 场效应晶体管（FET）包括第一漏极，第二漏极，主体和栅极区域。 栅极区域具有长度，并且被配置和布置成响应于栅极电压而产生在主体中，在第一和第二漏极之间以及沿着栅极区域的长度的沟道。 多个主体下拉位于栅极区域中并且沿着栅极区域的宽度间隔开。 每个身体下拉装置被构造和布置成为身体提供用于偏压目的的电接触。

公开(公告)号：US20140203365A1

公开(公告)日：2014-07-24

申请号：US14151576

申请日：2014-01-09

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Rob van Dalen ,  Erik Spaan

IPC: H01L27/06 ,  H01L21/8249 ,  H01L29/73

CPC classification number: H01L27/0623 ,  H01L21/76221 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7302

Abstract: There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer. The taper of the tapered insulating layer is in the lower surface of the tapered insulating layer. The tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer.

Abstract translation: 公开了一种半导体器件。 该装置包括：硅层; 形成在硅层上的锥形绝缘层; 以及形成在锥形绝缘层上方的多个双极CMOS DMOS器件层。 锥形绝缘层的锥度位于锥形绝缘层的下表面。 锥形绝缘层具有基本平坦的上表面，并且至少部分地凹入硅层中。