公开(公告)号：US11910598B2

公开(公告)日：2024-02-20

申请号：US17816299

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H10B41/27 ,  G11C5/02 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76838 ,  H01L23/5386 ,  H01L24/14 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11908538B2

公开(公告)日：2024-02-20

申请号：US17127091

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio

IPC: G11C5/14 ,  G11C5/06 ,  H01L23/538 ,  H01L23/50

CPC classification number: G11C5/14 ,  G11C5/06 ,  H01L23/50 ,  H01L23/5386

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

公开(公告)号：US20240055029A1

公开(公告)日：2024-02-15

申请号：US18447788

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei PENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO

IPC: G11C5/14 ,  G11C5/06 ,  H01L23/538 ,  H01L23/50

CPC classification number: G11C5/14 ,  G11C5/06 ,  H01L23/5386 ,  H01L23/50

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

公开(公告)号：US11894063B2

公开(公告)日：2024-02-06

申请号：US17695060

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Nayuta Kariya

IPC: G11C16/14 ,  G11C16/04 ,  G11C5/06 ,  G11C16/26 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/26 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, a second conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction, a third conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction and arranged with the second conductive layer in a second direction intersecting with the first direction, a first semiconductor column opposed to the first conductive layers and the second conductive layer, a second semiconductor column opposed to the first conductive layers and the third conductive layer, and a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction and a length of the third conductive layer in the second direction.

公开(公告)号：US11881283B2

公开(公告)日：2024-01-23

申请号：US17492336

申请日：2021-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Bong Chang

IPC: G11C7/10 ,  G11C5/06 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/1039 ,  G11C5/06 ,  G11C7/12 ,  G11C7/14

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

公开(公告)号：US11881279B2

公开(公告)日：2024-01-23

申请号：US17879479

申请日：2022-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Woon Park ,  Jae-Sang Yun

IPC: G11C5/06 ,  H01L23/00 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  H01L24/45

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

公开(公告)号：US11881256B2

公开(公告)日：2024-01-23

申请号：US17574655

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seoulmin Lee ,  Seokjin Cho

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4093

Abstract: A semiconductor memory device includes data pads, wordlines, memory cells, global input-output lines, and intra-bank switches. The wordlines extend in a row direction and are arranged in a column direction. The wordlines are grouped into wordline groups such that each wordline group includes wordlines adjacent in the column direction. A selection wordline is selected based on a row address. The global input-output lines extend in the column direction and are arranged in the row direction to transfer data between the data pads and the memory cells. The global input-output lines are cut into line segment groups respectively corresponding to the wordline groups. The intra-bank switches control, based on the row address, electrical connections between two line segment groups among the line segment groups, where the two line segment groups are adjacent in the column direction and included in one memory bank.

公开(公告)号：US20240004814A1

公开(公告)日：2024-01-04

申请号：US18369622

申请日：2023-09-18

Applicant: Lodestar Licensing Group LLC

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C5/02 ,  G06F13/42 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

CPC classification number: G06F13/1689 ,  G06F13/4068 ,  G11C5/06 ,  G11C5/02 ,  G06F13/42 ,  G11C7/1012 ,  G11C7/1069 ,  G11C11/4096 ,  G06F13/4234 ,  G11C5/04 ,  G11C5/063 ,  G11C11/4093

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US11837293B2

公开(公告)日：2023-12-05

申请号：US17898885

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/00 ,  G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20230380188A1

公开(公告)日：2023-11-23

申请号：US18361989

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Yuan-Tai Tseng

IPC: H10B63/00 ,  G11C5/06 ,  G11C13/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/00 ,  G11C5/06 ,  G11C13/0011 ,  H10N70/245 ,  H10N70/823

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.