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公开(公告)号:US12112830B2
公开(公告)日:2024-10-08
申请号:US17991489
申请日:2022-11-21
Applicant: Lodestar Licensing Group LLC
Inventor: Eric J. Stave , George E. Pax , Yogesh Sharma , Gregory A. King , Chan H. Yoo , Randon K. Richards , Timothy M. Hollis
CPC classification number: G11C7/222 , G11C7/1072 , G11C7/1093 , G11C16/10
Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
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公开(公告)号:US20240004814A1
公开(公告)日:2024-01-04
申请号:US18369622
申请日:2023-09-18
Applicant: Lodestar Licensing Group LLC
Inventor: Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G06F13/16 , G06F13/40 , G11C5/06 , G11C5/02 , G06F13/42 , G11C11/4093 , G11C7/10 , G11C11/4096 , G11C5/04
CPC classification number: G06F13/1689 , G06F13/4068 , G11C5/06 , G11C5/02 , G06F13/42 , G11C7/1012 , G11C7/1069 , G11C11/4096 , G06F13/4234 , G11C5/04 , G11C5/063 , G11C11/4093
Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
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公开(公告)号:US11789890B2
公开(公告)日:2023-10-17
申请号:US17850927
申请日:2022-06-27
Applicant: Lodestar Licensing Group LLC
Inventor: Thomas H. Kinsley , George E. Pax , Timothy M. Hollis , Yogesh Sharma , Randon K. Richards , Chan H. Yoo , Gregory A. King , Eric J. Stave
CPC classification number: G06F13/4234 , G06F11/1068 , G11C7/10
Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
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公开(公告)号:US20240126644A1
公开(公告)日:2024-04-18
申请号:US18397450
申请日:2023-12-27
Applicant: Lodestar Licensing Group LLC
Inventor: Martin Brox , Peter Mayer , Wolfgang Anton Spirkl , Thomas Hein , Michael Dieter Richter , Timothy M. Hollis , Roy Greeff
CPC classification number: G06F11/1004 , G06F11/16 , G06F12/02
Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
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公开(公告)号:US20240111707A1
公开(公告)日:2024-04-04
申请号:US18378000
申请日:2023-10-09
Applicant: Lodestar Licensing Group LLC
Inventor: Thomas H. Kinsley , George E. Pax , Timothy M. Hollis , Yogesh Sharma , Randon K. Richards , Chan H. Yoo , Gregory A. King , Eric J. Stave
CPC classification number: G06F13/4234 , G06F11/1068 , G11C7/10
Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
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公开(公告)号:US20240022457A1
公开(公告)日:2024-01-18
申请号:US18373122
申请日:2023-09-26
Applicant: Lodestar Licensing Group LLC
Inventor: Timothy M. Hollis
IPC: H04L25/03
CPC classification number: H04L25/03057
Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.
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公开(公告)号:US11860731B2
公开(公告)日:2024-01-02
申请号:US17857700
申请日:2022-07-05
Applicant: Lodestar Licensing Group LLC
Inventor: Martin Brox , Peter Mayer , Wolfgang Anton Spirkl , Thomas Hein , Michael Dieter Richter , Timothy M. Hollis , Roy E. Greeff
CPC classification number: G06F11/1004 , G06F11/16 , G06F12/02
Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
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公开(公告)号:US20240303194A1
公开(公告)日:2024-09-12
申请号:US18626212
申请日:2024-04-03
Applicant: Lodestar Licensing Group LLC
Inventor: Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G06F12/0806 , H04L5/00 , H04L27/14
CPC classification number: G06F12/0806 , H04L5/0007 , H04L27/14
Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
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公开(公告)号:US11971820B2
公开(公告)日:2024-04-30
申请号:US17863987
申请日:2022-07-13
Applicant: Lodestar Licensing Group LLC
Inventor: Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G06F12/08 , G06F12/0806 , H04L5/00 , H04L27/14
CPC classification number: G06F12/0806 , H04L5/0007 , H04L27/14
Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.