公开(公告)号：US20170358589A1

公开(公告)日：2017-12-14

申请号：US15672298

申请日：2017-08-09

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Pin-Yao Wang

IPC: H01L27/11524 ,  G11C8/14 ,  H01L21/308 ,  G11C16/12 ,  H01L21/28 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L27/11524 ,  G11C8/14 ,  G11C16/12 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/66553 ,  H01L29/66825

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

公开(公告)号：US09837159B2

公开(公告)日：2017-12-05

申请号：US15382862

申请日：2016-12-19

Applicant: SK hynix Inc.

Inventor： Hee Youl Lee

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

Abstract: Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.

公开(公告)号：US20170337976A1

公开(公告)日：2017-11-23

申请号：US15670220

申请日：2017-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinya OKUNO ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC: G11C16/32 ,  G06F13/16 ,  G06F5/06 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G06F2205/067 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/14

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US09824764B2

公开(公告)日：2017-11-21

申请号：US15258150

申请日：2016-09-07

Applicant: Toshiba Memory Corporation

Inventor： Yuki Kanamori ,  Yuji Nagai ,  Jun Nakai ,  Kenri Nakai

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N−1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

公开(公告)号：US09818486B2

公开(公告)日：2017-11-14

申请号：US15181251

申请日：2016-06-13

Applicant: Western Digital Technologies, Inc.

Inventor： Pablo A. Ziperovich

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14 ,  G11C16/12

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/12 ,  G11C16/14 ,  G11C16/3445

Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

公开(公告)号：US09805812B2

公开(公告)日：2017-10-31

申请号：US14668086

申请日：2015-03-25

Applicant: Donghun Kwak

Inventor： Donghun Kwak

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/16 ,  G11C11/56 ,  G11C16/12 ,  G11C29/02

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: An operating method of a storage device which includes a nonvolatile memory is provided. The operating method includes performing a first program operation on selected memory cells of the nonvolatile memory and storing a first time when the first program operation is performed; and adjusting a program parameter according to a difference between the first time and a second time, and performing a second program operation on the selected memory cells using the adjusted program parameter, the second time being a time when the second program operation is performed.

公开(公告)号：US09792996B1

公开(公告)日：2017-10-17

申请号：US15265810

申请日：2016-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroki Date

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/16 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3459

Abstract: According to one embodiment, a semiconductor memory device includes a word line and a driver. The word line coupled to a memory cell. The driver is configured to apply a voltage to the word line. When a voltage applied to the word line is changed from a first voltage to a second voltage, the driver applies a third voltage according to a voltage difference between the first voltage and the second voltage to the word line.

公开(公告)号：US20170271025A1

公开(公告)日：2017-09-21

申请号：US15455970

申请日：2017-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yuichiro SUZUKI ,  Noboru OOIKE ,  Masashi YOSHIDA

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.

公开(公告)号：US20170271017A1

公开(公告)日：2017-09-21

申请号：US15258150

申请日：2016-09-07

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yuki KANAMORI ,  Yuji NAGAI ,  Jun NAKAI ,  Kenri NAKAI

IPC: G11C16/12 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N−1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

公开(公告)号：US09754645B2

公开(公告)日：2017-09-05

申请号：US14924498

申请日：2015-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.