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公开(公告)号：US20240419369A1
公开(公告)日：2024-12-19
申请号：US18677892
申请日：2024-05-30
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Takehiro Kaminaga
IPC: G06F3/06
Abstract: An operating method of a semiconductor device including a NOR type flash memory and a NAND type flash memory is improved. A flash memory includes a NOR type flash memory, a NAND type flash memory, a controller, and an internal bus connecting the NOR type flash memory and the NAND type flash memory to the controller. The controller controls the NOR type flash memory, or the NOR type flash memory and the NAND type flash memory based on a command received from an outside.
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公开(公告)号：US11676662B2
公开(公告)日：2023-06-13
申请号：US17367641
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
CPC classification number: G11C13/0069 , G11C11/54 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0038
Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.
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公开(公告)号：US20220328105A1
公开(公告)日：2022-10-13
申请号：US17695852
申请日：2022-03-16
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: The disclosure provides a semiconductor device and an erasing method that may control a number of times an erase pulse is applied. The erasing method of a flash memory of the disclosure includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.
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公开(公告)号：US10978150B2
公开(公告)日：2021-04-13
申请号：US16548808
申请日：2019-08-22
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A memory circuit and a semiconductor device are provided. The memory circuit has a function of recovering data when power is suddenly shutdown. The memory device includes a bi-stable circuit capable of holding complementary data respectively at nodes N1 and N2; a first non-volatile memory circuit, connected to the node; and a second non-volatile memory circuit connected to the node. The first non-volatile memory circuit stores boot data, and the second non-volatile memory circuit inverts a logic level of the data held at the second node when the second non-volatile memory circuit stores data at the second node.
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5.发明授权
公开(公告)号：US10242950B2
公开(公告)日：2019-03-26
申请号：US15631889
申请日：2017-06-23
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Pin-Yao Wang
Abstract: A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.
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公开(公告)号：US20180247944A1
公开(公告)日：2018-08-30
申请号：US15892350
申请日：2018-02-08
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Riichiro Shirota
IPC: H01L27/1157 , H01L27/11582 , H01L27/11573
Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.
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公开(公告)号：US20170358589A1
公开(公告)日：2017-12-14
申请号：US15672298
申请日：2017-08-09
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Pin-Yao Wang
IPC: H01L27/11524 , G11C8/14 , H01L21/308 , G11C16/12 , H01L21/28 , H01L29/66 , H01L21/306
CPC classification number: H01L27/11524 , G11C8/14 , G11C16/12 , H01L21/28273 , H01L21/30604 , H01L21/3085 , H01L29/66553 , H01L29/66825
Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).
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公开(公告)号：US20170140826A1
公开(公告)日：2017-05-18
申请号：US15345521
申请日：2016-11-08
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3459
Abstract: A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.
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公开(公告)号：US20170117046A1
公开(公告)日：2017-04-27
申请号：US15141812
申请日：2016-04-28
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/10 , G11C7/02 , G11C7/18 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26
Abstract: A non-volatile semiconductor memory device having an improved layout structure to achieve low power consumption, high speed and miniaturization is provided. A flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. A plurality of local bit lines are shared by each of the plurality of blocks in one global block, a plurality of global bit lines are shared by the plurality of global blocks, and a connecting element selectively connecting one global bit line to n local bit lines is included. When a read-out operation and program operation are executed, one global bit line is shared by n local bit lines.
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公开(公告)号：US09275739B2
公开(公告)日：2016-03-01
申请号：US14332405
申请日：2014-07-16
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/10 , G11C16/0441 , G11C16/0483 , G11C16/26 , G11C16/28
Abstract: The invention provides a NAND-type semiconductor memory device capable of high speed operation. A semiconductor memory device of the invention includes: a memory array, which forms a plurality of memory cells arranged in a matrix direction; a vertical selecting mechanism, which couples to the memory array, and selects the memory cells in a vertical direction of the memory array according to a vertical address signal; a horizontal selecting mechanism, which couples to the memory array, and selects the memory cells in a horizontal direction of the memory array according to a horizontal address signal; and a controlling mechanism, which reads data from the memory cells or writes data into the memory cells. A plurality of cell units is disposed in the memory array. Each cell unit is consisted of a data memory cell which storages data and a reference memory cell which storages reference data.
Abstract translation: 本发明提供能够进行高速操作的NAND型半导体存储器件。 本发明的半导体存储器件包括：形成沿矩阵方向布置的多个存储单元的存储器阵列; 垂直选择机构，其耦合到存储器阵列，并根据垂直地址信号选择存储器阵列的垂直方向上的存储单元; 水平选择机构，其耦合到存储器阵列，并根据水平地址信号在存储器阵列的水平方向上选择存储单元; 以及从存储单元读取数据或将数据写入存储单元的控制机构。 多个单元单元设置在存储器阵列中。 每个单元单元由存储数据的数据存储单元和存储参考数据的参考存储单元组成。
