公开(公告)号：US20170337969A1

公开(公告)日：2017-11-23

申请号：US15410470

申请日：2017-01-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Go SHIKATA ,  Noboru OOIKE

IPC: G11C16/10 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/10 ,  G06F11/1068 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/52 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines, including a word line that is connected to a group of the memory cells, and a control circuit configured to execute a write operation on the memory cells of the group. The write operation includes multiple program loops including a first program loop and a second program loop that is executed at a later time than the first program loop, and for each subsequent program loop, a program voltage that is applied to the first word line is increased from that of a current program loop. The program voltage is increased by a first amount from that of the current program loop if the next program loop is the first program loop and by a second amount that is less than the first amount if the next program loop is the second program loop.

公开(公告)号：US20170271025A1

公开(公告)日：2017-09-21

申请号：US15455970

申请日：2017-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yuichiro SUZUKI ,  Noboru OOIKE ,  Masashi YOSHIDA

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.