公开(公告)号：US20230236974A1

公开(公告)日：2023-07-27

申请号：US18194716

申请日：2023-04-03

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC分类号： G06F12/0811 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802 ,  G06F12/126

CPC分类号： G06F12/0811 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/546 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/128 ,  G06F12/082 ,  G06F12/0804 ,  G06F9/3001 ,  G06F9/30047 ,  G11C7/106 ,  G11C7/1087 ,  G11C29/42 ,  G11C29/44 ,  G06F11/1064 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/1605 ,  G06F12/121 ,  G06F12/0292 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/222 ,  G11C7/1075 ,  G11C7/1078 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G06F15/8069 ,  G06F12/0802 ,  G06F9/30043 ,  G06F12/126 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/1024 ,  G06F2212/62 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6042

摘要： Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

公开(公告)号：US11709793B2

公开(公告)日：2023-07-25

申请号：US17827067

申请日：2022-05-27

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC分类号： G06T15/06 ,  G06F9/30 ,  G06F15/78 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0888 ,  G06N3/08

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Described herein is a graphics processing unit (GPU) comprising a first processing cluster to perform parallel processing operations, the parallel processing operations including a ray tracing operation and a matrix multiply operation; and a second processing cluster coupled to the first processing cluster, wherein the first processing cluster includes a floating-point unit to perform floating point operations, the floating-point unit is configured to process an instruction using a bfloat16 (BF16) format with a multiplier to multiply second and third source operands while an accumulator adds a first source operand with output from the multiplier.

公开(公告)号：US11693791B2

公开(公告)日：2023-07-04

申请号：US17377509

申请日：2021-07-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Naveen Bhoria ,  Timothy David Anderson ,  Pete Hippleheuser

IPC分类号： G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

CPC分类号： G06F12/0811 ,  G06F9/3001 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/082 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/128 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/62

摘要： A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

公开(公告)号：US11687460B2

公开(公告)日：2023-06-27

申请号：US15498076

申请日：2017-04-26

申请人： Advanced Micro Devices, Inc.

发明人： Michael W. LeBeane ,  Walter B. Benton ,  Vinay Agarwala

IPC分类号： G06F12/0817 ,  G06F12/1081 ,  G06F12/0831 ,  G06F12/0813 ,  G06F13/28

CPC分类号： G06F12/0828 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/154 ,  G06F2212/621 ,  G06F2212/622

摘要： Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which can receive the coherence information; GPU processing circuitry which can determine, based on the coherence information, whether the data satisfies a heuristic; and GPU loading circuitry which can load the data into a cache of the GPU from the main memory if on the data satisfies the heuristic.

公开(公告)号：US11663141B2

公开(公告)日：2023-05-30

申请号：US17068721

申请日：2020-10-12

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Daniel Brad Wu

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F9/48 ,  G06F9/46 ,  H03M13/15 ,  G06F12/1027 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/0891 ,  G06F12/0882

CPC分类号： G06F12/1027 ,  G06F9/467 ,  G06F9/4881 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  H03M13/1575 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/68

摘要： A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

公开(公告)号：US20190243783A1

公开(公告)日：2019-08-08

申请号：US16388955

申请日：2019-04-19

申请人： Oracle International Corporation

发明人： JUSTIN MATTHEW LEWIS ,  ZUOYU TAO ,  JIA SHI ,  KOTHANDA UMAMAGESWARAN

IPC分类号： G06F12/121 ,  G06F12/0891

CPC分类号： G06F12/121 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/466

摘要： Techniques are provided to adjust the behavior of a cache based on a count of cache misses for items recently evicted. In an embodiment, a computer responds to evicting a particular item (PI) from a cache by storing a metadata entry for the PI into memory. In response to a cache miss for the PI, the computer detects whether or not the metadata entry for the PI resides in memory. When the metadata entry for the PI is detected in memory, the computer increments a victim hit counter (VHC) that may be used to calculate how much avoidable thrashing is the cache experiencing, which is how much thrashing would be reduced if the cache were expanded. Either immediately or arbitrarily later, the computer adjusts a policy of the cache based on the VHC's value. For example, the computer may adjust the capacity of the cache based on the VHC.

公开(公告)号：US10359963B2

公开(公告)日：2019-07-23

申请号：US15532886

申请日：2017-01-23

申请人： Micron Technology, Inc.

发明人： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC分类号： G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

摘要： The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20190213141A1

公开(公告)日：2019-07-11

申请号：US16242912

申请日：2019-01-08

申请人： Apical Ltd ,  Arm Limited

发明人： Metin Gokhan ÜNAL ,  Kushan Vijaykumar VYAS ,  Robert SHORTER ,  Mario Jose DAVID MANZANO

IPC分类号： G06F12/121 ,  G06T1/60

CPC分类号： G06F12/121 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06T1/60

摘要： A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.

公开(公告)号：US20190171570A1

公开(公告)日：2019-06-06

申请号：US15829577

申请日：2017-12-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Duane Baldwin ,  Sasikanth Eda ,  John T. Olson ,  Sandeep R. Patil

IPC分类号： G06F12/0862 ,  G06F12/0895

CPC分类号： G06F12/0862 ,  G06F12/0895 ,  G06F16/172 ,  G06F2212/1021 ,  G06F2212/154 ,  G06F2212/6026 ,  H04L12/2854 ,  H04L67/104 ,  H04L67/2847

摘要： An embodiment of the invention may include a method, computer program product and system for optimizing a wide area network caching infrastructure in a file based object storage architecture. The embodiment may include creating, by a parent partition, a heat map. The embodiment may include prioritizing prefetching by multiple dependent partitions based on the heat map. In response to prioritized prefetching by the multiple dependent partitions, the embodiment may include allocating wide area network caching threads. The embodiment may include providing, by the parent partition, objects for prefetching by the multiple dependent partitions utilizing the allocated wide area network caching threads.

公开(公告)号：US20190116389A1

公开(公告)日：2019-04-18

申请号：US16215816

申请日：2018-12-11

申请人： Verizon Digital Media Services Inc.

发明人： Ravikiran Patil

IPC分类号： H04N21/231 ,  H04N21/2183 ,  H04N21/239

CPC分类号： H04N21/23106 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6026 ,  H04L67/2847 ,  H04N21/2183 ,  H04N21/2393 ,  H04N21/2408 ,  H04N21/8456

摘要： An adaptive stream segment prefetcher changes the number of segments it prefetches following a client requested segment of the same stream based on conditions associated with that stream at prefetch time. The adaptive prefetcher increases or decreases the number of segments to prefetch for a particular stream based on the number of active or concurrent clients requesting that particular stream, based on the playback duration of the particular stream by one or more clients, or some combination of both. The adaptive prefetcher continuously monitors the conditions associated with the stream such that number of segments prefetched at a first time are greater or less than the number of segments prefetched at a later second time.