公开(公告)号：US09299810B2

公开(公告)日：2016-03-29

申请号：US13935797

申请日：2013-07-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/785

Abstract: A fin-type field effect transistor includes a first fin including a first source, a first drain, and a first channel. The fin-type field effect transistor includes a second fin including a second source, a second drain, and a second channel. The fin-type field effect transistor includes a first semiconductor region under the first fin and a second semiconductor region under the second fin. A first reacted region is adjacent the first semiconductor region while a second reacted region is adjacent the second semiconductor region. The first reacted region has a first dimension causing a first strain in the first channel. The second reacted region has a second dimension causing a second strain in the second channel. The first strain and second strain are substantially equal to one another. A method of fabricating an example fin-type field effect transistor is provided.

Abstract translation: 翅片型场效应晶体管包括：第一鳍片，包括第一源极，第一漏极和第一沟道。 鳍型场效应晶体管包括：第二鳍片，包括第二源极，第二漏极和第二沟道。 鳍式场效应晶体管包括第一鳍片下方的第一半导体区域和第二鳍片下方的第二半导体区域。 第一反应区域与第一半导体区域相邻，而第二反应区域与第二半导体区域相邻。 第一反应区域具有在第一通道中引起第一应变的第一尺寸。 第二反应区域具有在第二通道中引起第二应变的第二维度。 第一应变和第二应变彼此基本相等。 提供一种制造示例性鳍型场效应晶体管的方法。

公开(公告)号：US20160056236A1

公开(公告)日：2016-02-25

申请号：US14929504

申请日：2015-11-02

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US20150200267A1

公开(公告)日：2015-07-16

申请号：US14461502

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

Abstract translation: 本文提供半导体器件和形成方法。 在一些实施例中，半导体器件包括具有掺杂区域的鳍。 半导体器件包括在鳍的通道部分上的栅极。 栅极包括在第一侧壁间隔物和第二侧壁间隔物之间​​的栅电介质上的栅电极。 第一侧壁间隔物包括介电材料的第一部分上的初始第一侧壁间隔物。 第二侧壁间隔物包括在电介质材料的第二部分上的初始第二侧壁间隔物。

公开(公告)号：US20150097227A1

公开(公告)日：2015-04-09

申请号：US14046960

申请日：2013-10-05

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pan Guo ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/76232 ,  H01L21/823878 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract translation: 半导体器件包括包括第一导电类型的第一类型区域。 半导体器件包括包括第二导电类型的第二类型区域。 半导体器件包括在第一类型区域和第二类型区域之间延伸的沟道区域。 半导体器件包括围绕沟道区的栅极区域。 栅极区域包括栅电极。 栅电极的栅电极长度小于约10nm。 提供一种形成半导体器件的方法。

公开(公告)号：US10361270B2

公开(公告)日：2019-07-23

申请号：US14084680

申请日：2013-11-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Cheng-Tung Lin ,  Kuo-Cheng Ching ,  Carlos H. Diaz

IPC: H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/16 ,  H01L21/265

Abstract: A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.

公开(公告)号：US10325989B2

公开(公告)日：2019-06-18

申请号：US15583981

申请日：2017-05-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/41 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L29/16

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US20180269321A1

公开(公告)日：2018-09-20

申请号：US15983444

申请日：2018-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.

公开(公告)号：US20180211884A1

公开(公告)日：2018-07-26

申请号：US15924350

申请日：2018-03-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US09935016B2

公开(公告)日：2018-04-03

申请号：US15463326

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US09634091B2

公开(公告)日：2017-04-25

申请号：US14929504

申请日：2015-11-02

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.