公开(公告)号：US20220262767A1

公开(公告)日：2022-08-18

申请号：US17736104

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L21/683 ,  H01L25/10

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

公开(公告)号：US20220230990A1

公开(公告)日：2022-07-21

申请号：US17153739

申请日：2021-01-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Po-Chen Lai ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution structure, a first die, a second die and a buffer layer. The second die is disposed between the first die and the redistribution structure, and the second die is electrically connected to the first die and bonded to the redistribution structure. The buffer layer is disposed on a first sidewall of the second die, wherein a second sidewall of the buffer layer is substantially flush with a third sidewall of the first die.

公开(公告)号：US20220208707A1

公开(公告)日：2022-06-30

申请号：US17699196

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US20220157777A1

公开(公告)日：2022-05-19

申请号：US17097059

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Chia Yang ,  Shu-Shen Yeh ,  Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

公开(公告)号：US11164754B2

公开(公告)日：2021-11-02

申请号：US16371917

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Tsai ,  Ming-Chih Yew ,  Chia-Kuei Hsu ,  Shin-Puu Jeng ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Shih-Ting Hung ,  Po-Yao Lin

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/522 ,  H01L25/10 ,  H01L23/538 ,  H01L23/367 ,  H01L23/13 ,  H01L23/31 ,  H01L23/482 ,  H01L23/488

Abstract: Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.

公开(公告)号：US11152323B2

公开(公告)日：2021-10-19

申请号：US16391022

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chien-Yu Li ,  Hung-Jui Kuo ,  Li-Hsien Huang ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chung-Shi Liu ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.

公开(公告)号：US20210296220A1

公开(公告)日：2021-09-23

申请号：US16823995

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11094646B2

公开(公告)日：2021-08-17

申请号：US16390877

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Clinton Chao ,  Szu-Wei Lu

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/52 ,  H01L21/78 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L23/58

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

公开(公告)号：US11081372B2

公开(公告)日：2021-08-03

申请号：US16712184

申请日：2019-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.

公开(公告)号：US11004771B2

公开(公告)日：2021-05-11

申请号：US16390669

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Chi-Hsi Wu ,  Shin-Puu Jeng ,  Tsung-Yu Chen ,  Wensen Hung

IPC: H01L23/427 ,  H01L23/367 ,  H01L23/373 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/34 ,  H01L23/31

Abstract: Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a cooling device for a semiconductor device includes a reservoir having a first plate and a second plate coupled to the first plate. A cavity is between the first plate and the second plate. A phase change material (PCM) is in the cavity. The cooling device is adapted to dissipate heat from a packaged semiconductor device.