知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

142 records (took 0.027 seconds)

    Method of making a FinFET device
    31.
    发明授权
    Method of making a FinFET device 有权
    制造FinFET器件的方法

    公开(公告)号：US09437497B2

    公开(公告)日：2016-09-06

    申请号：US14057789

    申请日：2013-10-18

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ming-Feng Shieh ,  Weng-Hung Tseng ,  Tzung-Hua Lin ,  Hung-Chang Hsieh

    IPC: H01L21/76 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

    CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886

    Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

    Abstract translation: 公开了制造鳍状场效应晶体管器件的方法。 该方法包括在基底上形成心轴特征并执行第一切割以去除心轴特征以形成第一空间。 该方法还包括执行第二切割以去除心轴特征的一部分以形成线端和端对端空间。 在第一次和第二次切割之后，使用芯棒特征蚀刻衬底，其中第一空间和端对端空间作为蚀刻掩模，以形成翅片。 沉积空间层以完全填充相邻散热片之间的空间并且覆盖与第一空间和端对端空间相邻的翅片的侧壁。 间隔层被蚀刻以在靠近第一空间和端对端空间的翅片上形成侧壁间隔物，并且在第一空间和端对端空间中形成隔离沟槽。

    Self-aligned semiconductor fabrication with fosse features
    33.
    发明授权
    Self-aligned semiconductor fabrication with fosse features 有权
    具有fosse特征的自对准半导体制造

    公开(公告)号：US09362169B2

    公开(公告)日：2016-06-07

    申请号：US14266878

    申请日：2014-05-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Tsai-Sheng Gau

    IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283

    Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

    Abstract translation: 本公开描述了将期望的布局转移到半导体衬底上的目标层中的方法。 所述方法的一个实施例包括在目标层上形成第一期望布局特征作为第一行; 在第一条线周围形成间隔物; 沉积间隔物周围的材料层; 去除所述间隔物以形成围绕所述第一线的顶点图案沟槽; 以及将所述花纹图案沟槽转移到所述目标层中，以在所述目标层中形成顶点特征沟槽，其中所述特征沟槽围绕所述目标层的位于保护层下方的第一部分。 在一些实施例中，该方法还包括将期望布局的第二所需布局特征图案化成目标层，其中，所述优点特征沟槽和所述保护层用于使所述第二期望布局特征与所述目标层的所述第一部分自对准。

    Lithography using high selectivity spacers for pitch reduction
    35.
    发明授权
    Lithography using high selectivity spacers for pitch reduction 有权
    使用高选择性间隔物的平版印刷法降低间距

    公开(公告)号：US09177797B2

    公开(公告)日：2015-11-03

    申请号：US14096864

    申请日：2013-12-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Sheng Chang ,  Chung-Ju Lee ,  Cheng-Hsiung Tsai ,  Yung-Hsu Wu ,  Hsiang-Huan Lee ,  Hai-Ching Chen ,  Ming-Feng Shieh ,  Tien-I Bao ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Shau-Lin Shue

    IPC: H01L21/311 ,  H01L21/033

    CPC classification number: H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

    Abstract translation: 用于图案化半导体器件的方法实施例包括在硬掩模上构图虚拟层以形成一个或多个虚拟线。 侧壁对齐的间隔件在一个或多个虚线和硬掩模上顺应地形成。 第一反向材料层形成在侧壁对齐的间隔物上。 在第一反向材料层上形成并图案化第一光致抗蚀剂。 使用第一光致抗蚀剂作为掩模的第一反向材料层，其中侧壁对齐的间隔物不被蚀刻。 去除一个或多个虚拟线，并且使用侧壁对准的间隔件和第一反向材料层作为掩模来对硬掩模进行图案化。 用于形成侧壁对准间隔物的材料比用于形成第一反向材料层的材料具有更高的选择性。

    PATTERNING METHOD FOR SEMICONDUCTOR DEVICE FABRICATION
    37.
    发明申请
    PATTERNING METHOD FOR SEMICONDUCTOR DEVICE FABRICATION 有权
    用于半导体器件制造的方法

    公开(公告)号：US20150270129A1

    公开(公告)日：2015-09-24

    申请号：US14729262

    申请日：2015-06-03

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yen-Chun Huang ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh

    IPC: H01L21/033 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/32

    CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming a first pattern having a first feature of a first material on a semiconductor substrate. A second pattern with a second feature and third feature of a second material, interposed by the first feature, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the first feature, the second feature, and the third feature. After forming the spacer elements, the second material comprising the second and third features is selectively removed to form a first opening and a second opening. The first feature, the first opening and the second opening are used as a masking element to etch the target layer.

    Abstract translation: 一种方法包括在半导体衬底上形成具有第一材料的第一特征的第一图案。 具有由第一特征插入的第二材料的第二特征和第三特征的第二图案形成在半导体衬底上。 间隔元件然后形成在第一特征，第二特征和第三特征的侧壁上。 在形成间隔元件之后，选择性地移除包括第二和第三特征的第二材料以形成第一开口和第二开口。 第一特征，第一开口和第二开口用作掩模元件以蚀刻目标层。

    MECHANISMS FOR FORMING PATTERNS
    38.
    发明申请
    MECHANISMS FOR FORMING PATTERNS 有权

    公开(公告)号：US20150147887A1

    公开(公告)日：2015-05-28

    申请号：US14090848

    申请日：2013-11-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Tsai-Sheng Gau ,  Shih-Ming Chang

    IPC: H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

    Method of making a FinFET device
    39.
    发明授权
    Method of making a FinFET device 有权
    制造FinFET器件的方法

    公开(公告)号：US09034723B1

    公开(公告)日：2015-05-19

    申请号：US14088861

    申请日：2013-11-25

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ming-Feng Shieh ,  Hung-Chang Hsieh ,  Han-Wei Wu

    IPC: H01L21/76 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31055 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a first cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.

    Abstract translation: 公开了制造鳍状场效应晶体管（FinFET）器件的方法。 多个心轴特征形成在基底上。 第一间隔件沿着心轴特征的侧壁形成，第二间隔件沿着第一间隔件的侧壁。 两个背对背相邻的第二间隔件通过第一区域中的间隙分开，并在基板的第二区域中合并在一起。 在间隙中形成电介质特征，并且在衬底的第三区域中形成电介质台面。 在第一切割中去除第一间隔物的第一子集。 通过使用第一间隔件和电介质特征作为蚀刻掩模蚀刻衬底来形成焊盘和沟槽。

Patent Agency Ranking