公开(公告)号：US10811537B2

公开(公告)日：2020-10-20

申请号：US16035476

申请日：2018-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Tze-Liang Lee ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/544 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.

公开(公告)号：US20190109194A1

公开(公告)日：2019-04-11

申请号：US16206500

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/167 ,  H01L21/02 ,  C30B29/06 ,  C23C16/02 ,  C30B25/18 ,  C23C16/44 ,  H01L29/66

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

公开(公告)号：US10026843B2

公开(公告)日：2018-07-17

申请号：US14954661

申请日：2015-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Tze-Liang Lee ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L23/544

Abstract: A method for manufacturing an active region of a semiconductor device includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the substrate. The top surface of the substrate is baked. An epitaxial layer is formed on the top surface of the substrate.

公开(公告)号：US12027605B2

公开(公告)日：2024-07-02

申请号：US18362281

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/822

CPC classification number: H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66787 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/8221 ,  H01L29/516

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US12009427B2

公开(公告)日：2024-06-11

申请号：US17978027

申请日：2022-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/3115 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02255

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

公开(公告)号：US11854910B2

公开(公告)日：2023-12-26

申请号：US17663608

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/84 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/76256 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1211

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

公开(公告)号：US20230395437A1

公开(公告)日：2023-12-07

申请号：US18447948

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/84 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/845 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1211 ,  H01L21/76256

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

公开(公告)号：US11791397B2

公开(公告)日：2023-10-17

申请号：US18175180

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7853 ,  H01L21/0228 ,  H01L21/02181 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

公开(公告)号：US11769818B2

公开(公告)日：2023-09-26

申请号：US17815033

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/822

CPC classification number: H01L29/6653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/6681 ,  H01L29/66787 ,  H01L29/7853 ,  H01L21/8221 ,  H01L29/516

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US10658468B2

公开(公告)日：2020-05-19

申请号：US16206500

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tetsuji Ueno ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L21/00 ,  H01L29/167 ,  H01L21/02 ,  C23C16/02 ,  C30B25/18 ,  C30B29/06 ,  C23C16/44 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.