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    System on chip
    31.
    发明授权
    System on chip 有权

    公开(公告)号：US10050032B2

    公开(公告)日：2018-08-14

    申请号：US15416016

    申请日：2017-01-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Semiconductor device and method of fabricating the same
    33.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US09640444B2

    公开(公告)日：2017-05-02

    申请号：US14807220

    申请日：2015-07-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sang-Kyu Oh ,  Kwanyoung Chun ,  Sunyoung Park ,  Taejoong Song

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

    CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

    Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

    Semiconductor devices and methods of forming the same
    34.
    发明授权
    Semiconductor devices and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09449970B2

    公开(公告)日：2016-09-20

    申请号：US14829650

    申请日：2015-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Moo-Gyu Bae ,  Taejoong Song

    IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118

    CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0642 ,  H01L2027/11874

    Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.

    Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。

    Semiconductor device including a field effect transistor
    36.
    发明授权
    Semiconductor device including a field effect transistor 有权

    公开(公告)号：US11557585B2

    公开(公告)日：2023-01-17

    申请号：US17154282

    申请日：2021-01-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

    IPC: H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398 ,  G06F119/18

    Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

    Semiconductor device
    40.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10134838B2

    公开(公告)日：2018-11-20

    申请号：US15820053

    申请日：2017-11-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myoung-Ho Kang ,  Jung-Ho Do ,  Giyoung Yang ,  Seungyoung Lee

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

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