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公开(公告)号：US12217645B2
公开(公告)日：2025-02-04
申请号：US18136630
申请日：2023-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD. , CHUNG ANG University Industry Academic Cooperation Foundation
Inventor： Unjeong Kim , Hojung Kim , Hyungbin Son , Suyeon Lee
Abstract: An operating method of a calibration system for a display device obtains image information about an image displayed on display device and wavelength information about pixels of the image information using a hyperspectral camera included in an electronic device, transmits the obtained image information and wavelength information to a first application in the electronic device, generates calibration data about the obtained image information and wavelength information through the first application and transmits the calibration data to a second application in the display device, and performs color calibration of the display device based on the calibration data transmitted to the second application to display a color calibrated image.
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公开(公告)号：US20220262968A1
公开(公告)日：2022-08-18
申请号：US17459686
申请日：2021-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chanwook Baik , Kyungsang Cho , Hojung Kim , Yooseong Yang
IPC: H01L31/0384 , H01L31/112 , H01L31/113 , H01L27/146 , H01L31/0216
Abstract: An opto-electronic device includes a base portion, a first electrode and a second electrode formed on an upper surface of the base portion apart from each other, a quantum dot layer, and a bank structure. The quantum dot layer is between the first electrode and the second electrode on the base portion and includes a plurality of quantum dots. The bank structure covers at least partial regions of the first electrode and the second electrode, defines a region where the quantum dot layer is formed, and is formed of an inorganic material.
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公开(公告)号：US11302740B2
公开(公告)日：2022-04-12
申请号：US16930574
申请日：2020-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungsang Cho , Chanwook Baik , Hojung Kim
IPC: H01L31/0352 , H01L31/0384 , H01L31/112 , H01L27/146
Abstract: Provided is an opto-electronic device having low dark noise and a high signal-to-noise ratio. The opto-electronic device may include: a first semiconductor layer doped to have a first conductivity type; a second semiconductor layer disposed on an upper surface of the first semiconductor layer and doped to have a second conductivity type electrically opposite to the first conductivity type; a transparent matrix layer disposed on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to be in contact with the transparent matrix layer; and a first electrode provided on a first side of the transparent matrix layer and a second electrode provided on a second side of the transparent matrix layer opposite to the first side, wherein the first electrode and the second electrode are electrically connected to the second semiconductor layer.
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公开(公告)号：US10783717B2
公开(公告)日：2020-09-22
申请号：US15455400
申请日：2017-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojung Kim , Yongkyu Kim , Hoon Song , Hongseok Lee
IPC: G06T19/20 , G06F17/14 , H04N13/271 , H04N13/161 , G03H1/08 , G06T7/262 , H04N7/18
Abstract: A method for processing a three-dimensional (3D) image includes acquiring a frame of a color image and a frame of a depth image, and generating a frame by combining the acquired frame of the color image with the acquired frame of the depth image. The generating of the frame includes combining a line of the color image with a corresponding line of the depth image.
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公开(公告)号：US09953579B2
公开(公告)日：2018-04-24
申请号：US14833387
申请日：2015-08-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojung Kim , Seunghoon Han , Hoon Song , Hongseok Lee
CPC classification number: G09G3/3266 , G02B27/017 , G02B2027/0178 , G03H1/02 , G03H1/2294 , G03H2001/0224 , G03H2225/21 , G09G3/34 , G09G2300/08 , G09G2310/0264
Abstract: An acousto-optic element array includes: acousto-optic elements each including an acousto-optic generator, a light supply, and a wave transducer; a gate driver that selects an acousto-optic element to be driven from among the acousto-optic elements; an electrical data driver that is connected to an electrical wire and transmits electrical data to an electro-optic modulator configured to control the acousto-optic generator of the selected acousto-optic element; and a wave data driver that is connected to a waveguide and transmits wave data to the wave transducer of the selected acousto-optic element.
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Patent Agency Ranking
公开(公告)号：US09837009B2
公开(公告)日：2017-12-05
申请号：US14564966
申请日：2014-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojung Kim , Hongseok Lee
CPC classification number: G09G3/20 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2300/08 , G09G2310/0205 , G09G2310/0262 , G09G2320/0223 , G09G2320/0252 , H01L27/1225 , H01L27/124
Abstract: An apparatus for driving a display panel including a plurality of cells coupled to a plurality of gate lines and a plurality of data lines, a gate driver configured to output a gate selection signal to a shared gate line, and a data driver configured to output data signals to the cell array. The shared gate line includes a first gate line and a second gate line, the first and second gate lines sharing the gate selection signal.
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公开(公告)号：US09773802B2
公开(公告)日：2017-09-26
申请号：US15209371
申请日：2016-07-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Xianyu Wenxu , Inkyeong Yoo , Hojung Kim , Seong ho Cho
IPC: H01L29/792 , H01L27/1157 , H01L21/28 , H01L21/02 , H01L21/762 , H01L21/308 , H01L29/08 , H01L29/06 , G11C11/54 , H01L29/68 , H01L45/00 , H01L29/66 , H01L27/105
CPC classification number: H01L27/1157 , G11C11/54 , G11C11/5685 , G11C13/0007 , G11C2213/53 , G11C2213/79 , H01L21/0217 , H01L21/02175 , H01L21/02183 , H01L21/02186 , H01L21/28282 , H01L21/308 , H01L21/762 , H01L21/76202 , H01L21/76224 , H01L27/1052 , H01L29/0649 , H01L29/0847 , H01L29/66833 , H01L29/685 , H01L45/00
Abstract: Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.
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公开(公告)号：US09755313B2
公开(公告)日：2017-09-05
申请号：US14830335
申请日：2015-08-19
Inventor： Chulsoon Park , Hojung Kim , Hongyi Kim , Innyeal Oh , Joongho Lee , Taehwan Jang
CPC classification number: H01Q9/28 , H01Q1/2283
Abstract: Provided are chip antennas for near field communication and methods of manufacturing the chip antennas. A chip antenna for near field communication includes a substrate; a first antenna element on the substrate; and a second antenna element on the first antenna element. The substrate, the first antenna element, and the second antenna element are included in a single chip. The first and second antenna elements are formed outside the chip. The substrate is a lower layer including a plurality of devices. The first antenna element is a metal structure having a fish bone shape. The second antenna element is a dipole antenna.
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公开(公告)号：US09747985B2
公开(公告)日：2017-08-29
申请号：US15206791
申请日：2016-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Inkyeong Yoo , Hojung Kim , Seongho Cho
IPC: G11C16/04 , H01L27/11568 , H01L23/528 , H01L45/00 , G11C16/10 , G11C16/26 , G11C16/14
CPC classification number: G11C16/0466 , G11C16/0433 , G11C16/045 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28273 , H01L23/528 , H01L27/11521 , H01L27/11568 , H01L29/42324
Abstract: A non-volatile inverter may be configured to perform a memory function. The non-volatile inverter may include first and second transistors. The first transistor may include a first gate electrode, a first electrode, and a second electrode. The second transistor may include a second gate electrode and a third electrode and may share the second electrode with the first transistor. The first transistor may include a first switching layer and a charge trap layer. The first switching layer may be configured to switch between a high resistance state and a low resistance state. The charge trap layer may be configured to trap or de-trap charges according to the resistance state of the first switching layer. The first switching layer may include a P-N diode. The second transistor may include a second gate switching layer and a charge trap layer.
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公开(公告)号：US09727970B2
公开(公告)日：2017-08-08
申请号：US14636934
申请日：2015-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoon Song , Hojung Kim , Juwon Seo , Hongseok Lee
CPC classification number: G03H1/0808 , G03H1/2294 , G03H2001/0228 , G03H2001/2271 , G03H2210/454 , G03H2226/02
Abstract: A method of generating a hologram includes receiving three-dimensional (3D) image data, dividing 3D image data into data groups which are independent from one another, by a first processor; calculating, from at least one of the data groups, hologram values to be displayed at respective positions on a hologram plane, by the first processor; calculating, from at least another one of the data groups, hologram values to be displayed at the respective positions on the hologram plane by a second processor, and summing the calculated hologram values for each of the respective positions on the hologram plane, by the first processor or the second processor, or by the first processor and the second processor in parallel.
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