公开(公告)号：US09773802B2

公开(公告)日：2017-09-26

申请号：US15209371

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xianyu Wenxu ,  Inkyeong Yoo ,  Hojung Kim ,  Seong ho Cho

IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/308 ,  H01L29/08 ,  H01L29/06 ,  G11C11/54 ,  H01L29/68 ,  H01L45/00 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L27/1157 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/53 ,  G11C2213/79 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66833 ,  H01L29/685 ,  H01L45/00

Abstract: Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.