公开(公告)号：US10032678B2

公开(公告)日：2018-07-24

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L21/8234

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

公开(公告)号：US20180114848A1

公开(公告)日：2018-04-26

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09953979B2

公开(公告)日：2018-04-24

申请号：US14673485

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Junjing Bao ,  John Jianhong Zhu ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L21/70 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/768 ,  H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/285 ,  H01L21/76897 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

公开(公告)号：US09799560B2

公开(公告)日：2017-10-24

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

公开(公告)号：US09793164B2

公开(公告)日：2017-10-17

申请号：US14939561

申请日：2015-11-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: G06F17/50 ,  G06F19/00 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/76897 ,  G06F17/5068 ,  G06F17/5077 ,  G06F19/00 ,  G06F2217/12 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/53228

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

公开(公告)号：US09721891B2

公开(公告)日：2017-08-01

申请号：US15378633

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing Bao ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Niladri Narayan Mojumder ,  Choh Fei Yeap

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes an aluminum oxide barrier layer. The aluminum oxide barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

公开(公告)号：US09698267B2

公开(公告)日：2017-07-04

申请号：US14320897

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Mohamed Hassan Abu-Rahma ,  Beom-Mo Han

IPC: H01L29/786 ,  H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  G11C11/40

CPC classification number: H01L29/785 ,  G11C11/40 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7841 ,  H01L29/7855 ,  H01L29/78648

Abstract: A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.

公开(公告)号：US09666481B2

公开(公告)日：2017-05-30

申请号：US15141198

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20170110364A1

公开(公告)日：2017-04-20

申请号：US15390405

申请日：2016-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  John Jianhong Zhu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.

公开(公告)号：US09607988B2

公开(公告)日：2017-03-28

申请号：US14611090

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Stanley Seungchul Song

IPC: H01L21/70 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/0847

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.