公开(公告)号：US20200312786A1

公开(公告)日：2020-10-01

申请号：US16362951

申请日：2019-03-25

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Kai LIU ,  Xia LI

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

公开(公告)号：US20200066858A1

公开(公告)日：2020-02-27

申请号：US16112484

申请日：2018-08-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Ye LU ,  Bin YANG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

Abstract: A thin film transistor may include an insulating substrate and a layer of semiconductor material disposed over the insulating substrate. The thin film transistor may further include a gate electrode, a source electrode and a drain electrode disposed over the insulating substrate. The thin film transistor may further include a layer of first dielectric material disposed in between the gate electrode and the source and drain electrodes, and a layer of second dielectric material in contact with the layer of first dielectric material. The second dielectric material has a negative index.

公开(公告)号：US20190245058A1

公开(公告)日：2019-08-08

申请号：US16384234

申请日：2019-04-15

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI

IPC: H01L29/66 ,  H01L29/737 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L29/66318 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/49568 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.

公开(公告)号：US20190051750A1

公开(公告)日：2019-02-14

申请号：US15676494

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.

公开(公告)号：US20180366592A1

公开(公告)日：2018-12-20

申请号：US15686827

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Chuan-Hsing CHEN ,  Bin YANG ,  Lixin GE ,  Ken LIAO

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/66 ,  H01L29/4232 ,  H01L29/456 ,  H01L29/66174 ,  H01L29/66181

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

公开(公告)号：US20180342513A1

公开(公告)日：2018-11-29

申请号：US15663602

申请日：2017-07-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L27/092 ,  H01L29/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

公开(公告)号：US20180337269A1

公开(公告)日：2018-11-22

申请号：US15599157

申请日：2017-05-18

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H03F3/213 ,  H03F1/30 ,  H03F3/195 ,  G01K7/01

Abstract: A heterojunction bipolar transistor (HBT) thermal sensing device includes a well structure as a layer between an HBT sub-collector and an HBT substrate. In one instance, the HBT sub-collector contacts an emitter, a collector, and a base of the HBT thermal sensing device. The HBT thermal sensing device also includes a first side electrode in electrical contact with the quantum well structure and a second side electrode in electrical contact with the quantum well structure.

公开(公告)号：US20160013306A1

公开(公告)日：2016-01-14

申请号：US14858992

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Ming CAI

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/15 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/7789 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/151 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7781 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses.

Abstract translation: 高带隙材料的内翅片在基板上，具有两个垂直面，并被低带隙材料的载流子再分布翅片围绕。 内鳍和载体再分布鳍具有两个垂直接口。 载流子再分布片相对于内鳍的带隙具有厚度和带隙，沿着两个垂直界面建立相应的两个二维电子气体的平衡。

公开(公告)号：US20150035039A1

公开(公告)日：2015-02-05

申请号：US14044725

申请日：2013-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Seung Hyuk KANG

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：US20220359611A1

公开(公告)日：2022-11-10

申请号：US17313834

申请日：2021-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.