公开(公告)号：US11462611B2

公开(公告)日：2022-10-04

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US20220093483A1

公开(公告)日：2022-03-24

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US10727330B2

公开(公告)日：2020-07-28

申请号：US16598115

申请日：2019-10-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861

Abstract: A semiconductor device includes a SiC body having a first surface, a gate trench extending from the first surface into the SiC body and having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, a source region of a first conductivity type formed in the SiC body and adjoining the first sidewall of the gate trench, a drift region of the first conductivity type formed in the SiC body below the source region, a body region of a second conductivity type formed in the SiC body between the source region and the drift region and adjoining the first sidewall of the gate trench, and a diode region of the second conductivity type formed in the SiC body and adjoining the second sidewall and the bottom of the gate trench but not the first sidewall of the gate trench.

公开(公告)号：US10580878B1

公开(公告)日：2020-03-03

申请号：US16105742

申请日：2018-08-20

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Rudolf Elpelt ,  Romain Esteve

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16

Abstract: A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer.

公开(公告)号：US20200058760A1

公开(公告)日：2020-02-20

申请号：US16105742

申请日：2018-08-20

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Rudolf Elpelt ,  Romain Esteve

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10

Abstract: A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer.

公开(公告)号：US10553685B2

公开(公告)日：2020-02-04

申请号：US15959661

申请日：2018-04-23

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Daniel Kueck

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

公开(公告)号：US20190355819A1

公开(公告)日：2019-11-21

申请号：US16412131

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US20180294260A1

公开(公告)日：2018-10-11

申请号：US16001540

申请日：2018-06-06

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/40

CPC classification number: H01L27/0664 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

Abstract: A semiconductor device with a trench gate structure in a semiconductor body with a hexagonal crystal lattice is disclosed. In an embodiment a semiconductor device includes a semiconductor body with a hexagonal crystal lattice, wherein a mean surface plane of a first surface of the semiconductor body is tilted with respect to a crystal direction of the hexagonal crystal lattice by an off-axis angle, a trench gate structure extending into the semiconductor body and at least two transistor mesas formed from portions of the semiconductor body and adjoining the trench gate structure, wherein sidewalls of the at least two transistor mesas are aligned with a (11-20) crystal plane and deviate from a normal to the mean surface plane by at most 5 degrees, and wherein each transistor mesa comprises a MOS gate channel.

公开(公告)号：US09837527B2

公开(公告)日：2017-12-05

申请号：US14957116

申请日：2015-12-02

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/872 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/36 ,  H01L29/861

CPC classification number: H01L29/7806 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.

公开(公告)号：US09741712B2

公开(公告)日：2017-08-22

申请号：US15053117

申请日：2016-02-25

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L27/06 ,  H01L29/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/40

CPC classification number: H01L27/0664 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

Abstract: A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.