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公开(公告)号：US09449827B2
公开(公告)日：2016-09-20
申请号：US14172526
申请日：2014-02-04
IPC分类号： H01L21/28 , H01L29/45 , H01L29/78 , H01L21/285 , H01L29/66 , H01L23/485 , H01L23/532 , H01L21/768
CPC分类号： H01L21/28026 , H01L21/28512 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L23/485 , H01L23/53238 , H01L29/456 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.
摘要翻译： 接触开口形成为露出半导体衬底的表面部分的电介质材料。 包括至少一个第一过渡金属元件的第一过渡金属衬垫，包括与所述至少一个第一过渡金属元件不同的至少一个第二过渡金属元件和金属接触件的第二过渡金属衬垫在每个接触开口 。 在平坦化处理之后，结构是在每个接触开口的底部处退火形成金属半导体合金触头。 形成的每个金属半导体合金触点包括至少一个第一过渡金属元件，至少一个第二过渡金属元件和半导体元件。
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32.发明授权公开(公告)号：US09425309B2
公开(公告)日：2016-08-23
申请号：US14483923
申请日：2014-09-11
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L29/45 , H01L29/66 , H01L29/78 , H01L21/285 , H01L21/311 , H01L21/768 , H01L21/02 , H01L29/49 , H01L21/3205 , H01L21/321 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
摘要翻译： 提供一种半导体器件，其包括在衬底的沟道区上的栅极结构。 源极区域和漏极区域存在于沟道区域的相对侧上。 第一金属半导体合金存在于源区和漏区中的至少一个的上表面上。 第一金属半导体合金延伸到栅极结构的侧壁。 介电层存在于栅极结构和第一金属半导体合金之上。 存在通过电介质层到与栅极结构分离的第一金属半导体合金的一部分的开口。 第二金属半导体合金存在于开口中，与第一金属半导体合金直接接触，并且具有垂直偏移的上表面并且位于第一金属半导体合金的上表面之上。
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公开(公告)号：US20160027889A1
公开(公告)日：2016-01-28
申请号：US14876924
申请日：2015-10-07
IPC分类号： H01L29/45
CPC分类号： H01L29/456 , H01L21/268 , H01L21/28512 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L23/53266 , H01L29/41725 , H01L2924/0002 , H01L2924/00
摘要： A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening.
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公开(公告)号：US20150270222A1
公开(公告)日：2015-09-24
申请号：US14223592
申请日：2014-03-24
IPC分类号： H01L23/532 , H01L27/092 , H01L21/285 , H01L29/423 , H01L29/417 , H01L29/78 , H01L23/535
CPC分类号： H01L21/76886 , H01L21/28518 , H01L21/28568 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/76895 , H01L21/823871 , H01L23/485 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/092 , H01L29/41766 , H01L29/665 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.
摘要翻译： 接触开口形成为露出半导体衬底的表面部分的电介质材料。 然后在每个接触开口中和界面氧化物层的暴露表面部分上形成界面氧化物层。 在每个开口内和每个界面氧化物层的暴露的表面部分上形成NiPt合金层。 然后进行退火，其形成从底部到顶部具有倒金字塔形状，富Pt硅化物帽区域和富氧区域的二硅化镍合金体的接触结构。 然后在每个接触开口内和每个接触结构的富氧区顶上形成金属接触。
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公开(公告)号：US20150270178A1
公开(公告)日：2015-09-24
申请号：US14219193
申请日：2014-03-19
发明人： Emre Alptekin , Nicolas L. Breil , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg , Keith Kwong Hon Wong
IPC分类号： H01L21/8238 , H01L21/324 , H01L29/45 , H01L21/285 , H01L27/092
CPC分类号： H01L21/823871 , H01L21/268 , H01L21/28512 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53266 , H01L27/092 , H01L27/0922 , H01L29/41725 , H01L29/456 , H01L2924/0002 , H01L2924/00
摘要： A contact can be formed by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material that exposes the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film having a first and second type of metal and a second metal film. The metal stack and the silicon-containing region of the semiconductor substrate are annealed to form a silicide that includes the first and second types of metal and that is in contact with the semiconductor substrate. A first liner is formed within the opening and a fill metal is deposited in the opening.
摘要翻译： 可以通过在半导体衬底的含硅区域上形成介电材料层来形成接触。 通过暴露含硅区域的介电材料层产生开口。 在开口内形成金属叠层。 金属叠层至少包括具有第一和第二类金属的第一金属膜和第二金属膜。 对半导体衬底的金属叠层和含硅区进行退火以形成包含第一和第二类金属并与半导体衬底接触的硅化物。 第一衬里形成在开口内，并且填充金属沉积在开口中。
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公开(公告)号：US08987135B2
公开(公告)日：2015-03-24
申请号：US13908624
申请日：2013-06-03
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L21/44 , H01L21/768 , H01L21/285 , H01L23/485 , H01L29/45 , H01L29/66
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
摘要翻译： 一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。 将混合后的金属半导体区域退火以形成织构化的金属半导体合金。 在纹理金属半导体合金上形成第二金属层。 纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。 模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。
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37.发明申请FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS 审中-公开具有合金金属半导体合金区域的FIN场效应晶体管公开(公告)号：US20150076607A1
公开(公告)日：2015-03-19
申请号：US14029830
申请日：2013-09-18
发明人： Emre Alptekin , Aysa M. Ozbek , Ahmet S. Ozcan , Yiyi Wang
CPC分类号： H01L29/785 , H01L21/283 , H01L21/28518 , H01L23/485 , H01L29/0847 , H01L29/41791 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures.
摘要翻译： 具有多面半导体表面的凸起的活性区域通过选择性外延形成在半导体鳍片上，使得凸起的有源区域彼此不相互合并，但是彼此接近距离小于之后的金属半导体合金区域的厚度 形成。 通过使金属材料与凸起的活性区域的半导体材料沉积和反应来形成连续的金属半导体合金区域。 连续的金属半导体合金区域与多个凸起的有源区域的成角度的表面接触，并且可以提供比包括具有相似尺寸的合并的半导体鳍片的半导体结构更大的接触面积和更低的寄生接触电阻。 合并翅片使得可以采用比总共凸起的有源区域更小和/或更少的接触通孔结构，以减少栅电极和接触通孔结构之间的寄生电容。
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公开(公告)号：US20140306290A1
公开(公告)日：2014-10-16
申请号：US13860743
申请日：2013-04-11
发明人： Emre Alptekin , Siyuranga O. Koswatta , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg , Paul M. Solomon , Zhen Zhang
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/41725 , H01L29/41766 , H01L29/66545
摘要： In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s).
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公开(公告)号：US20140210011A1
公开(公告)日：2014-07-31
申请号：US13755427
申请日：2013-01-31
发明人： Ashish K. Baraskar , Cyril Cabral , Siyuranga O. Koswatta , Christian Lavoie , Ahmet S. Ozcan , Li Yang , Zhen Zhang
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/84 , H01L27/092 , H01L27/1203
摘要： In one aspect, a method for silicidation includes the steps of: (a) providing a wafer having at least one first active area and at least one second active area defined therein; (b) masking the first active area with a first hardmask; (c) doping the second active area; (d) forming a silicide in the second active area, wherein the first hardmask serves to mask the first active area during both the doping step (c) and the forming step (d); (e) removing the first hardmask; (f) masking the second active area with a second hardmask; (g) doping the first active area; (h) forming a silicide in the first active area, wherein the second hardmask serves to mask the second active area during both the doping step (g) and the forming step (h); and (i) removing the second hardmask.
摘要翻译： 一方面，一种用于硅化的方法包括以下步骤：（a）提供具有限定在其中的至少一个第一有源区和至少一个第二有源区的晶片; （b）用第一硬掩模掩蔽所述第一活动区域; （c）掺杂第二活性区; （d）在所述第二有源区中形成硅化物，其中所述第一硬掩模用于在所述掺杂步骤（c）和所述形成步骤（d）期间掩蔽所述第一有源区; （e）移除第一个硬掩模; （f）用第二硬掩模掩蔽所述第二活动区域; （g）掺杂第一活性区; （h）在所述第一有源区中形成硅化物，其中所述第二硬掩模用于在所述掺杂步骤（g）和所述形成步骤（h）期间掩蔽所述第二有源区; 和（i）移除第二个硬掩模。
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公开(公告)号：US08603881B1
公开(公告)日：2013-12-10
申请号：US13623292
申请日：2012-09-20
发明人： Emre Alptekin , Ahmet S. Ozcan , Viraj Y. Sardesai , Cung D. Tran
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/28518 , H01L21/28525 , H01L21/2855 , H01L21/76814 , H01L21/76829 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A contact via hole is formed through at least one dielectric layer over a semiconductor substrate. A semiconductor material is deposited at the bottom of the contact via hole and atop the at least one dielectric layer by ion cluster deposition. An angled oxygen cluster deposition is performed to convert portions of the semiconductor material on the top surface of the at least one dielectric layer into a semiconductor oxide, while oxygen is not implanted into the deposited semiconductor material at the bottom of the contact via hole. A metal semiconductor alloy is formed at the bottom of the contact hole by deposition of a metal and an anneal. The semiconductor oxide at the top of the at least one dielectric layer can be removed during a preclean before metal deposition, a postclean after metal semiconductor alloy formation, and/or during planarization for forming contact via structures.
摘要翻译： 通过半导体衬底上的至少一个电介质层形成接触通孔。 半导体材料通过离子簇沉积沉积在接触通孔的底部和至少一个电介质层顶上。 执行成角度的氧簇沉积，以将至少一个电介质层的顶表面上的半导体材料的部分转换成半导体氧化物，同时在接触通孔的底部没有将氧气注入到沉积的半导体材料中。 通过沉积金属和退火在接触孔的底部形成金属半导体合金。 在金属沉积之前的预清洗期间，在金属半导体合金形成后的后清洗中和/或在用于形成接触通孔结构的平坦化期间，可以去除在至少一个介电层顶部的半导体氧化物。
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