FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS
    1.
    发明申请
    FIN FIELD EFFECT TRANSISTOR WITH MERGED METAL SEMICONDUCTOR ALLOY REGIONS 审中-公开
    具有合金金属半导体合金区域的FIN场效应晶体管

    公开(公告)号:US20150076607A1

    公开(公告)日:2015-03-19

    申请号:US14029830

    申请日:2013-09-18

    IPC分类号: H01L29/78 H01L29/66

    摘要: Raised active regions having faceted semiconductor surfaces are formed on semiconductor fins by selective epitaxy such that the raised active regions are not merged among one another, but are proximal to one another by a distance less than a thickness of a metal semiconductor alloy region to be subsequently formed. A contiguous metal semiconductor alloy region is formed by depositing and reacting a metallic material with the semiconductor material of raised active regions. The contiguous metal semiconductor alloy region is in contact with angled surfaces of the plurality of raised active regions, and can provide a greater contact area and lower parasitic contact resistance than a semiconductor structure including merged semiconductor fins of comparable sizes. Merged fins enable smaller, and/or fewer, contact via structures than a total number of raised active regions can be employed to reduce parasitic capacitance between a gate electrode and the contact via structures.

    摘要翻译: 具有多面半导体表面的凸起的活性区域通过选择性外延形成在半导体鳍片上,使得凸起的有源区域彼此不相互合并,但是彼此接近距离小于之后的金属半导体合金区域的厚度 形成。 通过使金属材料与凸起的活性区域的半导体材料沉积和反应来形成连续的金属半导体合金区域。 连续的金属半导体合金区域与多个凸起的有源区域的成角度的表面接触,并且可以提供比包括具有相似尺寸的合并的半导体鳍片的半导体结构更大的接触面积和更低的寄生接触电阻。 合并翅片使得可以采用比总共凸起的有源区域更小和/或更少的接触通孔结构,以减少栅电极和接触通孔结构之间的寄生电容。

    METHOD TO IMPROVE SEMICONDUCTOR SURFACES AND POLISHING
    4.
    发明申请
    METHOD TO IMPROVE SEMICONDUCTOR SURFACES AND POLISHING 有权
    改善半导体表面和抛光的方法

    公开(公告)号:US20150044869A1

    公开(公告)日:2015-02-12

    申请号:US14522011

    申请日:2014-10-23

    IPC分类号: H01L21/768 H01L21/3213

    摘要: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

    摘要翻译: 公开了一种形成半导体器件的方法。 所述方法包括提供其上设置有至少一个绝缘层的衬底,所述至少一个绝缘层包括沟槽; 在所述至少一个绝缘层上形成至少一个衬垫层; 在所述至少一个衬垫层上形成成核层; 在成核层的表面上形成第一金属膜; 蚀刻第一金属膜; 以及在所述第一金属膜的蚀刻表面上沉积第二金属膜,所述第二金属膜基本上在所述沟槽上形成覆盖层。