公开(公告)号：US20150262869A1

公开(公告)日：2015-09-17

申请号：US14276879

申请日：2014-05-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Mehul B. NAIK ,  Srinivas D. NEMANI ,  Takehito KOSHIZAWA ,  He REN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/32136 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/02071 ,  H01L21/02274 ,  H01L21/32139 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76885

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract translation: 本发明的实施例提供了在半导体器件中形成互连结构而不破坏最小氧化/大气暴露的真空的方法。 在一个实施例中，用于形成用于半导体器件的互连结构的方法包括将阻挡层蚀刻气体混合物供应到具有设置在其中的衬底的第一处理室中，以蚀刻由图案化金属层暴露的阻挡层的部分，直到下面的衬底为 暴露的第一处理室，设置在处理系统中，并且在布置在处理系统中的第二处理室中，在覆盖蚀刻的阻挡层的基板上形成衬垫层。

公开(公告)号：US20150262834A1

公开(公告)日：2015-09-17

申请号：US14642340

申请日：2015-03-09

Applicant: APPLIED MATERIALS, INC.

Inventor： Sergey G. BELOSTOTSKIY ,  Chinh DINH ,  Qingjun ZHOU ,  Srinivas D. NEMANI ,  Andrew NGUYEN

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/263

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/263

Abstract: A method for etching a dielectric layer disposed on a substrate is provided. The method includes de-chucking the substrate from an electrostatic chuck in an etching processing chamber, and cyclically etching the dielectric layer while the substrate is de-chucked from the electrostatic chuck. The cyclical etching includes remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the dielectric layer disposed on the substrate at a first temperature. Etching the dielectric layer generates etch byproducts. The cyclical etching also includes vertically moving the substrate towards a gas distribution plate in the etching processing chamber, and flowing a sublimation gas from the gas distribution plate towards the substrate to sublimate the etch byproducts. The sublimation is performed at a second temperature, wherein the second temperature is greater than the first temperature.

Abstract translation: 提供了一种用于蚀刻设置在基板上的电介质层的方法。 该方法包括在蚀刻处理室中从静电卡盘取下基板，并在基板从静电卡盘脱卡的同时循环蚀刻电介质层。 循环蚀刻包括在提供到蚀刻处理室中的蚀刻气体混合物中远程产生等离子体，以在第一温度下蚀刻设置在基板上的电介质层。 蚀刻介电层产生蚀刻副产物。 循环蚀刻还包括将衬底垂直移动到蚀刻处理室中的气体分配板，并且使升华气体从气体分配板朝向衬底流动以升华蚀刻副产物。 升华在第二温度下进行，其中第二温度大于第一温度。

公开(公告)号：US20150179581A1

公开(公告)日：2015-06-25

申请号：US14268727

申请日：2014-05-02

Applicant: Applied Materials, Inc.

Inventor： Yihong CHEN ,  Abhijit Basu MALLICK ,  Mehul B. NAIK ,  Srinivas D. NEMANI

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

Abstract translation: 提供一种用于形成用于半导体器件的互连结构的方法。 该方法首先在衬底上形成低k体积电介质层，然后在低k体电介质层中形成沟槽。 衬底层形成在与沟槽共形沉积的低k体积电介质层上。 在填充沟槽的衬垫层上形成铜层。 去除部分铜层和衬层以形成低k体电介质层，衬里层和铜层的上表面。 在低k体电介质层，衬垫层和铜层的上表面上形成含金属的电介质层。

公开(公告)号：US20150056814A1

公开(公告)日：2015-02-26

申请号：US14059416

申请日：2013-10-21

Applicant: Applied Materials, Inc.

Inventor： Mang-Mang LING ,  Jungmin KO ,  Sean S. KANG ,  Jeremiah T. PENDER ,  Srinivas D. NEMANI ,  Bradley HOWARD

IPC: H01L21/3065 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/31116 ,  H01J2237/334 ,  H01L21/76802

Abstract: Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.

Abstract translation: 提供了使用主蚀刻步骤和循环蚀刻工艺的组合蚀刻设置在基板上的材料层的方法。 该方法包括在处理室中对氧化物层进行主蚀刻处理，在氧化物层中形成具有第一预定深度的特征，通过将处理气体混合物供应到处理室中来对衬底进行处理，以处理 在所述氧化物层中蚀刻特征，通过向所述处理室中提供化学蚀刻气体混合物，在所述基板上进行化学蚀刻处理，其中所述化学蚀刻气体至少包含铵气体和三氟化氮，其中所述化学蚀刻工艺进一步蚀刻 将特征提供到第二预定深度，并且通过将过渡气体混合物供应到处理室中来对蚀刻的基板执行转变处理。

公开(公告)号：US20240085810A1

公开(公告)日：2024-03-14

申请号：US18243129

申请日：2023-09-07

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh Ashok BANGAR ,  Chih-An HSU ,  Srinivas D. NEMANI ,  Dmitry LUBOMIRSKY ,  Ellie Y. YIEH

IPC: G03F7/00 ,  G03F7/40

CPC classification number: G03F7/70875 ,  G03F7/40

Abstract: A method and apparatus for performing post-exposure bake operations is described herein. After exposure of photoresist on a substrate, the substrate is heated during a baking process to facilitate protection of the resist. The baking process is performed in a vacuum environment at sub-atmospheric pressures. After baking at reduced pressure, the substrate is cooled. The cooling process is performed at sub-atmospheric pressures. Further development of the resist is performed at ambient pressures.

公开(公告)号：US20230229089A1

公开(公告)日：2023-07-20

申请号：US18188676

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh Ashok BANGAR ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Steven Hiloong WELCH ,  Christopher S. NGAI

IPC: G03F7/039 ,  G03F7/004

CPC classification number: G03F7/0392 ,  G03F7/0045

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20220317579A1

公开(公告)日：2022-10-06

申请号：US17222696

申请日：2021-04-05

Applicant: Applied Materials, Inc.

Inventor： Mangesh Ashok BANGAR ,  Gautam PISHARODY ,  Lancelot HUANG ,  Alan L. TSO ,  Douglas A. BUCHBERGER, JR. ,  Huixiong DAI ,  Dmitry LUBOMIRSKY ,  Srinivas D. NEMANI ,  Christopher Siu Wing Ngai

IPC: G03F7/20

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for verification and re-use of process fluids. The apparatus generally includes a tool for performing lithography, and a recirculation path coupled to the tool. The recirculation path generally includes a collection unit coupled at first end to a first end of the tool, and a probe coupled at a first end to a second end of the collection unit, the probe for determining one or more characteristics of a fluid flowing from the tool. The recirculation path of the apparatus further generally includes a purification unit coupled at a first end to a third end of the collection unit, the purification unit further coupled at a second end to a second end of the probe, the purification unit for changing a characteristic of the fluid.

公开(公告)号：US20220230887A1

公开(公告)日：2022-07-21

申请号：US17150280

申请日：2021-01-15

Applicant: Applied Materials, Inc.

Inventor： Meiyee SHEK ,  Maximillian CLEMONS ,  Srinivas D. NEMANI ,  Nikolaos BEKIARIS ,  Ellie YIEH

IPC: H01L21/311

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method includes heating a substrate disposed in an interior volume of a process chamber and having a boron-containing film deposited thereon to a predetermined temperature; and supplying water vapor in a non-plasma state to the interior volume at a predetermined pressure for a predetermined time, while maintaining the substrate at the predetermined temperature to anneal the substrate for the predetermined time and remove the boron-containing film.

公开(公告)号：US20210384040A1

公开(公告)日：2021-12-09

申请号：US17408943

申请日：2021-08-23

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. CITLA ,  Jethro TANNOS ,  Jingyi LI ,  Douglas A. BUCHBERGER, JR. ,  Zhong Qiang HUA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/311 ,  H01L21/762 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  C23C16/515 ,  H01L21/02 ,  C23C16/509 ,  C23C16/517 ,  C23C16/505

Abstract: Embodiments of the present invention provide an apparatus and methods for depositing a dielectric material using RF bias pulses along with remote plasma source deposition for manufacturing semiconductor devices, particularly for filling openings with high aspect ratios in semiconductor applications. In one embodiment, a method of depositing a dielectric material includes providing a gas mixture into a processing chamber having a substrate disposed therein, forming a remote plasma in a remote plasma source and delivering the remote plasma to an interior processing region defined in the processing chamber, applying a RF bias power to the processing chamber in pulsed mode, and forming a dielectric material in an opening defined in a material layer disposed on the substrate in the presence of the gas mixture and the remote plasma.

公开(公告)号：US20210294215A1

公开(公告)日：2021-09-23

申请号：US16825388

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Srinivas D. NEMANI ,  Steven Hiloong WELCH ,  Mangesh Ashok BANGAR ,  Ellie Y. YIEH

IPC: G03F7/20 ,  H01L21/266 ,  H01L21/027 ,  H01L21/311 ,  G03F7/16 ,  G03F7/38

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.