公开(公告)号：US20240204104A1

公开(公告)日：2024-06-20

申请号：US18591730

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US12002719B2

公开(公告)日：2024-06-04

申请号：US18083757

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US20240177996A1

公开(公告)日：2024-05-30

申请号：US18412173

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive

公开(公告)号：US20240170563A1

公开(公告)日：2024-05-23

申请号：US18154975

申请日：2023-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Shu-Han Chen ,  Chi On Chui

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66545

Abstract: A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source/drain region is aside of the gate stack.

公开(公告)号：US20240170536A1

公开(公告)日：2024-05-23

申请号：US18425895

申请日：2024-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02631

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

公开(公告)号：US20240162303A1

公开(公告)日：2024-05-16

申请号：US18418678

申请日：2024-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/78696 ,  H01L21/823807

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US11974441B2

公开(公告)日：2024-04-30

申请号：US17138152

申请日：2020-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0653 ,  H01L29/0669 ,  H10B51/10

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

公开(公告)号：US11967504B2

公开(公告)日：2024-04-23

申请号：US17532204

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Kun-Yu Lee ,  Chi On Chui

IPC: H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/0262

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

公开(公告)号：US11942549B2

公开(公告)日：2024-03-26

申请号：US18064562

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US11942523B2

公开(公告)日：2024-03-26

申请号：US18168422

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7834 ,  H01L29/78696 ,  H01L21/30604 ,  H01L21/3065

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.