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    Semiconductor device and methods of forming the same
    2.
    发明授权
    Semiconductor device and methods of forming the same 有权

    公开(公告)号：US12243786B2

    公开(公告)日：2025-03-04

    申请号：US17744334

    申请日：2022-05-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Da-Yuan Lee ,  Chi On Chui

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

    Dielectric Layer for Nanosheet Protection and Method of Forming the Same
    3.
    发明公开
    Dielectric Layer for Nanosheet Protection and Method of Forming the Same 审中-公开

    公开(公告)号：US20240170563A1

    公开(公告)日：2024-05-23

    申请号：US18154975

    申请日：2023-01-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Shu-Han Chen ,  Chi On Chui

    IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

    CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66545

    Abstract: A device includes a gate stack having a top portion, and a stacked structure underlying the top portion of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, with upper nanostructures in the plurality of semiconductor nanostructures overlapping respective lower nanostructures. The stacked structure further includes a plurality of gate structures, each including a lower portion of the gate stack. Each of the plurality of gate structures is between two of the plurality of semiconductor nanostructures. A dielectric layer extends on a top surface and a sidewall of the stacked structure. The dielectric layer includes a lower sub layer comprising a first dielectric material, and an upper sub layer over the lower sub layer and formed of a second dielectric material different from the first dielectric material. A gate spacer is on the dielectric layer. A source/drain region is aside of the gate stack.

    Dielectric Gap-Filling Process for Semiconductor Device
    6.
    发明申请
    Dielectric Gap-Filling Process for Semiconductor Device 有权

    公开(公告)号：US20220384248A1

    公开(公告)日：2022-12-01

    申请号：US17818382

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Bang-Tai Tang

    IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

    Dielectric gap-filling process for semiconductor device
    8.
    发明授权
    Dielectric gap-filling process for semiconductor device 有权

    公开(公告)号：US12198974B2

    公开(公告)日：2025-01-14

    申请号：US18351985

    申请日：2023-07-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Bang-Tai Tang

    IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

    SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20230282524A1

    公开(公告)日：2023-09-07

    申请号：US17744334

    申请日：2022-05-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Da-Yuan Lee ,  Chi On Chui

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L21/823821

    Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

    Dielectric gap-filling process for semiconductor device
    10.
    发明授权
    Dielectric gap-filling process for semiconductor device 有权

    公开(公告)号：US11488855B2

    公开(公告)日：2022-11-01

    申请号：US16983647

    申请日：2020-08-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-I Lin ,  Bang-Tai Tang

    IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

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