公开(公告)号：US12087767B2

公开(公告)日：2024-09-10

申请号：US18068647

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US12069865B2

公开(公告)日：2024-08-20

申请号：US17567586

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US12068162B2

公开(公告)日：2024-08-20

申请号：US17874670

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31053 ,  H01L21/76227 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

公开(公告)号：US12058870B2

公开(公告)日：2024-08-06

申请号：US17868278

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/78 ,  H01L29/786 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/78696 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.

公开(公告)号：US20240260276A1

公开(公告)日：2024-08-01

申请号：US18612267

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/06 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H01L29/78391 ,  H10B51/10

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

公开(公告)号：US12046519B2

公开(公告)日：2024-07-23

申请号：US17882165

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L21/28568

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US12041786B2

公开(公告)日：2024-07-16

申请号：US17933650

申请日：2022-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Chi On Chui

IPC: H01L27/11507 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B53/30

CPC classification number: H10B53/30 ,  H01L28/60 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.

公开(公告)号：US12033853B2

公开(公告)日：2024-07-09

申请号：US18446953

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02356 ,  H01L21/02181 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/76829 ,  H01L21/76871 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

公开(公告)号：US20240213347A1

公开(公告)日：2024-06-27

申请号：US18598934

申请日：2024-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

公开(公告)号：US12020941B2

公开(公告)日：2024-06-25

申请号：US18356860

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/3115 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/513 ,  H01L21/823431

Abstract: A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.