公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US12079123B2

公开(公告)日：2024-09-03

申请号：US18094549

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher J. Bueb ,  Ashok Sahoo

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F2212/7205

Abstract: A host system can be queried to determine whether new data has been received based on a first time interval. After completion of the first time interval, a determination can be made as to whether the new data has been received and whether a portion of the new data was not stored. In response to the portion of the new data not being stored, the host system can be queried to determine whether subsequent data has been received based on a second time interval where the second time interval is different from first time interval.

公开(公告)号：US20240281372A1

公开(公告)日：2024-08-22

申请号：US18653814

申请日：2024-05-02

Applicant: Micron Technology, Inc.

Inventor： Antonio David Bianco ,  John Paul Traver

IPC: G06F12/02 ,  G06F9/54 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F9/546 ,  G06F12/0253 ,  G06F12/0891 ,  G06F2212/7209

Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.

公开(公告)号：US20240281369A1

公开(公告)日：2024-08-22

申请号：US18581270

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0261 ,  G06F13/1668

Abstract: Methods, systems, and devices for a partitioned cache for random read operations are described. Implementations may determine a target compression factor that is used during read operations. Larger compression factors may be associated with more frequent penalties, but may allow for a larger high-performance benchmark on a large address range. As described herein, a compression factor may indicate certain mappings that are stored to a volatile memory. The compression factor may be chosen at product design time or may be chosen dynamically at run time based on statistics such as extended cache hit or miss rate. If a read command associated with a logical block address not stored by the volatile memory is received, the memory system may “guess” the physical address by assuming that data was written to the memory system sequentially. If the data is correct, the data may be read out to the host system.

公开(公告)号：US20240281171A1

公开(公告)日：2024-08-22

申请号：US18589184

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US12066892B2

公开(公告)日：2024-08-20

申请号：US18184395

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

IPC: G06F11/10 ,  G06F3/06 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0882

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F9/30029 ,  G06F11/1076 ,  G06F12/0246 ,  G06F12/0882

Abstract: An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.

公开(公告)号：US20240272967A1

公开(公告)日：2024-08-15

申请号：US18643656

申请日：2024-04-23

Applicant: Micron Technology, Inc.

Inventor： John Traver ,  Jay R. Shoen

IPC: G06F9/54 ,  G06F9/38 ,  G06F12/02 ,  G06F12/084 ,  G06F12/0871

CPC classification number: G06F9/544 ,  G06F9/3836 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/084 ,  G06F12/0871

Abstract: Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

公开(公告)号：US20240264957A1

公开(公告)日：2024-08-08

申请号：US18425079

申请日：2024-01-29

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Donghyun GOUK ,  Miryeong KWON

IPC: G06F13/16 ,  G06F12/02 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F12/0246 ,  G06F13/4221

Abstract: A compute express link (CXL) computing system includes a host device including a CPU that supports CXL, and a CXL storage connected to a CXL root port of the CPU based on the CXL interconnect and including a flash memory-based memory module.

公开(公告)号：US12056047B2

公开(公告)日：2024-08-06

申请号：US17937334

申请日：2022-09-30

Applicant: SK hynix Inc.

Inventor： Jung Woo Kim

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F13/1668

Abstract: A memory system may include a memory device including a plurality of memory blocks each including a plurality of pages and a memory controller. The memory controller may be configured to determine a plurality of super memory blocks each including two or more of the plurality of memory blocks, calculate valid page counts of each of the plurality of super memory blocks, and determine a victim block for garbage collection based on a minimum value among the valid page counts of the plurality of super memory blocks and average value of the valid page counts of the plurality of super memory blocks. Furthermore, a dispersion of valid page counts of memory block groups within the super memory blocks may be used to determine the victim block.

公开(公告)号：US20240256468A1

公开(公告)日：2024-08-01

申请号：US18633149

申请日：2024-04-11

Applicant: Lodestar Licensing Group, LLC.

Inventor： Nadav Grosz ,  Jonathan Scott Parry

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/78

CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F21/78 ,  G06F2212/7201

Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.