公开(公告)号：US20130105861A1

公开(公告)日：2013-05-02

申请号：US13286222

申请日：2011-11-01

Applicant: Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

IPC: H01L21/205 ,  H01L27/088

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Abstract translation: 半导体器件包括半导体衬底和多个晶体管。 半导体衬底至少包括一个iso区域（即开放区域）和至少一个致密区域。 晶体管分别设置在iso区域和致密区域中。 每个晶体管至少包括一个源极/漏极区域。 源极/漏极区域包括具有底部厚度和侧部厚度的第一外延层，并且底部厚度基本上大于或等于侧部厚度。

公开(公告)号：US20130078780A1

公开(公告)日：2013-03-28

申请号：US13241188

申请日：2011-09-22

Applicant: Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成中间层。 在中间层上形成第一金属氧化物层。 进行还原处理以将第一金属氧化物层还原成金属层。 执行高温处理以将金属层转变为第二金属氧化物层。

公开(公告)号：US20120329261A1

公开(公告)日：2012-12-27

申请号：US13164781

申请日：2011-06-21

Applicant: Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

Inventor： Shao-Wei Wang ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Wen-Yi Teng ,  Tsuo-Wen Lu ,  Chih-Chung Chen ,  Ying-Wei Yen ,  Yu-Min Lin ,  Chin-Cheng Chien ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Yi-Ching Wu ,  Shu-Yen Chan

IPC: H01L21/782 ,  H01L21/28

CPC classification number: H01L29/7833 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract translation: 一种金属栅极的制造方法，包括提供具有至少形成有导电类型的半导体器件的衬底，在该半导体器件中形成栅极沟槽，形成具有导电类型的功函数金属层和对应于 栅极沟槽中的导电类型，并且执行离子注入以将功函数金属层的固有功函数调整到目标功函数。

公开(公告)号：US20120299157A1

公开(公告)日：2012-11-29

申请号：US13115125

申请日：2011-05-25

Applicant: Teng-Chun Hsuan ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan

Inventor： Teng-Chun Hsuan ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan

IPC: H01L29/02 ,  H01L21/28

CPC classification number: H01L21/31116 ,  H01L21/0206 ,  H01L21/28123 ,  H01L21/76232

Abstract: A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 提供了一种衬底，其包括隔离结构和氧化物层。 隔离结构将衬底划分成第一区域和第二区域。 氧化物层位于第一区域和第二区域的表面上。 进行干洗处理以除去氧化物层。 在第一区域和第二区域上形成介电层。 执行湿蚀刻处理以去除位于第一区域和第二区域上的介电层中的至少一个。 通过上述半导体工艺制造半导体结构。

公开(公告)号：US20120270377A1

公开(公告)日：2012-10-25

申请号：US13092990

申请日：2011-04-25

Applicant: Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chan-Lon Yang ,  Chun-Yuan Wu

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chan-Lon Yang ,  Chun-Yuan Wu

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/324 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7834

Abstract: A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.

Abstract translation: 一种制造半导体结构的方法，其中在进行蚀刻处理以在栅极结构之外的半导体内形成至少一个凹槽时，在包含惰性气体的气体气氛中的凹部上进行热处理， 通过外延生长工艺在凹部中形成含有外延层的外延层。

公开(公告)号：US20120070995A1

公开(公告)日：2012-03-22

申请号：US12886580

申请日：2010-09-21

Applicant: Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

Inventor： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC: H01L21/302

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US20110086499A1

公开(公告)日：2011-04-14

申请号：US12577729

申请日：2009-10-13

Applicant: Chin-Cheng Chien ,  Chan-Lon Yang ,  Chiu-Hsien Yeh

Inventor： Chin-Cheng Chien ,  Chan-Lon Yang ,  Chiu-Hsien Yeh

IPC: H01L21/265 ,  H01L21/306

CPC classification number: H01L21/31133 ,  G03F7/423 ,  H01L21/266

Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.

Abstract translation: 公开了一种去除光致抗蚀剂的方法。 首先，提供包括图案化光致抗蚀剂的基板。 其次，在基板上进行离子注入。 然后，在基板上进行非氧化性预处理。 非氧化预处理提供氢气，载气和等离子体。 之后，进行光致抗蚀剂剥离工序，使光致抗蚀剂能够被完全除去。

公开(公告)号：US20080233722A1

公开(公告)日：2008-09-25

申请号：US11690138

申请日：2007-03-23

Applicant: Chin-I Liao ,  Chin-Cheng Chien ,  Hou-Jun Wu ,  Po-Lun Cheng

Inventor： Chin-I Liao ,  Chin-Cheng Chien ,  Hou-Jun Wu ,  Po-Lun Cheng

IPC: H01L33/00

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.

Abstract translation: 提供一种形成选择性区域半导体化合物外延层的方法。 该方法包括使用两个含硅前体作为气体源的步骤，用于实现制造选择性区域半导体化合物外延层的工艺，以便在衬底的暴露的单晶硅区域上形成半导体化合物外延层。

公开(公告)号：US07034905B2

公开(公告)日：2006-04-25

申请号：US10463553

申请日：2003-06-18

Applicant: Wen-Jyh Sah ,  Chin-Cheng Chien

Inventor： Wen-Jyh Sah ,  Chin-Cheng Chien

IPC: G02F1/1333

CPC classification number: G02F1/1309 ,  G02F2001/136272

Abstract: A liquid crystal display panel is provided. The LCD panel has a first substrate having at least a conductive material layer thereon, a second substrate having at least a repair line positioned in a predetermined area, and a liquid crystal layer positioned between the first substrate and the second substrate. The predetermined area is underneath the first substrate excluding the portions having the conductive material layer, thus reducing RC delay of the repair line.

Abstract translation: 提供液晶显示面板。 LCD面板具有至少具有导电材料层的第一基板，至少具有位于预定区域中的修复线的第二基板和位于第一基板和第二基板之间的液晶层。 预定区域在除了具有导电材料层的部分之外的第一基板的下方，从而减少修复线的RC延迟。

公开(公告)号：US20050164461A1

公开(公告)日：2005-07-28

申请号：US10764437

申请日：2004-01-27

Applicant: Yu-Kun Chen ,  Neng-Hui Yang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang

Inventor： Yu-Kun Chen ,  Neng-Hui Yang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/2256 ,  H01L21/28176 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.

Abstract translation: 公开了一种用于形成半导体器件的接合区域的方法。 该方法的步骤包括提供半导体衬底。 栅极结构形成在半导体衬底上。 将掺杂剂注入到半导体衬底中以形成结区域。 在栅极结构和半导体衬底上形成绝缘体层。 对绝缘体层进行含碳等离子体处理。 在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。 对半导体基板进行热处理。