公开(公告)号：US20080293213A1

公开(公告)日：2008-11-27

申请号：US11774811

申请日：2007-07-09

Applicant: Neng Hui Yang ,  Hai Jun Zhao

Inventor： Neng Hui Yang ,  Hai Jun Zhao

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/76235

Abstract: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

公开(公告)号：US06943085B2

公开(公告)日：2005-09-13

申请号：US10667229

申请日：2003-09-17

Applicant: Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/6656 ,  H01L29/66666

Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

公开(公告)号：US06893909B2

公开(公告)日：2005-05-17

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US20050074931A1

公开(公告)日：2005-04-07

申请号：US10681768

申请日：2003-10-07

Applicant: Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chun-Yi Lee ,  Yu-Kun Chen ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/28035 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract translation: 提供一种制造MOS晶体管的方法。 栅极绝缘层和导电层依次形成在衬底上。 进行前非晶化注入以使导电层非晶化。 将导电层和栅极绝缘层图案化以形成栅极结构。 在栅极结构的侧壁上形成第一间隔物。 进行第二次非晶化植入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。 在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

公开(公告)号：US20050054173A1

公开(公告)日：2005-03-10

申请号：US10667229

申请日：2003-09-17

Applicant: Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

Inventor： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/331

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/6656 ,  H01L29/66666

Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

Abstract translation: 提供一种制造MOS晶体管的方法。 提供其上具有栅极结构的衬底。 在栅极结构的侧壁上形成第一间隔物。 进行预非晶化注入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 第二间隔件形成在第一间隔件的侧壁上。 在第二间隔物的每一侧上的衬底中形成掺杂的源/漏区，然后进行预退火操作。 此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。 最后，执行后退火操作。

公开(公告)号：US06861104B2

公开(公告)日：2005-03-01

申请号：US10063896

申请日：2002-05-22

Applicant: Hsin-Chang Wu ,  Cheng-Yuan Tsai ,  Yu-Wen Fang ,  Neng-Hui Yang

Inventor： Hsin-Chang Wu ,  Cheng-Yuan Tsai ,  Yu-Wen Fang ,  Neng-Hui Yang

IPC: H01L21/308 ,  H01L21/316 ,  B05D3/06 ,  C23C14/10 ,  C23C14/14 ,  H01L21/306 ,  H01L21/473 ,  H05H1/46

CPC classification number: H01L21/02129 ,  H01L21/02315 ,  H01L21/3081 ,  H01L21/31625

Abstract: A method of enhancing adhesion strength of a boro-silicate glass (BSG) film to a silicon nitride film is provided. A semiconductor substrate with a silicon nitride film formed thereon is provided. The silicon nitride film is then exposed to oxygen-containing plasma such as ozone plasma. A thick BSG film is then deposited onto the treated surface of the silicon nitride film. By pre-treating the silicon nitride film with ozone plasma for about 60 seconds, an increase of near 50% of Kapp of the BSG film is obtained.

Abstract translation: 提供了一种提高硼硅酸盐玻璃（BSG）膜对氮化硅膜的粘附强度的方法。 提供其上形成有氮化硅膜的半导体衬底。 然后将氮化硅膜暴露于含氧等离子体如臭氧等离子体。 然后将厚的BSG膜沉积在氮化硅膜的处理表面上。 通过用臭氧等离子体预处理氮化硅膜约60秒，可获得BSG膜的Kapp近50％的增加。

公开(公告)号：US06653204B1

公开(公告)日：2003-11-25

申请号：US10248749

申请日：2003-02-14

Applicant: Hsin-Chang Wu ,  Neng-Hui Yang ,  Cheng-Yuan Tsai ,  Wen-Hsun Lin

Inventor： Hsin-Chang Wu ,  Neng-Hui Yang ,  Cheng-Yuan Tsai ,  Wen-Hsun Lin

IPC: H01L2176

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76224

Abstract: A pad oxide layer and a silicon nitride (SiN) layer are sequentially formed on a silicon substrate. An etching process is then performed to form a trench in the silicon substrate. A sub-atmospheric chemical vapor deposition (SACVD) process is performed to selectively form a first dielectric layer on exposed portions of the silicon substrate within the trench to fill portions of the trench thereafter. Finally, a high density plasma chemical vapor deposition (HDPCVD) process is performed to form a second dielectric layer to fill the remaining space of the trench and cover the silicon substrate.

Abstract translation: 衬垫氧化物层和氮化硅（SiN）层依次形成在硅衬底上。 然后进行蚀刻工艺以在硅衬底中形成沟槽。 执行亚大气压化学气相沉积（SACVD）工艺以选择性地在沟槽内的硅衬底的暴露部分上形成第一介电层，以此之后填充部分沟槽。 最后，进行高密度等离子体化学气相沉积（HDPCVD）工艺以形成第二介质层以填充沟槽的剩余空间并覆盖硅衬底。

公开(公告)号：US06521545B1

公开(公告)日：2003-02-18

申请号：US09682822

申请日：2001-10-23

Applicant: Neng-Hui Yang ,  Chinh-Fu Lin ,  Yi-Fang Cheng ,  Cheng-Yuan Tsai

Inventor： Neng-Hui Yang ,  Chinh-Fu Lin ,  Yi-Fang Cheng ,  Cheng-Yuan Tsai

IPC: H01L2126

CPC classification number: H01L21/3105

Abstract: The invention shows a method of a surface treatment on a fluorine silicate glass film. At first a fluorine silicate glass layer is deposited on a semiconductor wafer. Partial fluorine ions in the fluorine silicate glass layer are in-situ removed to form a silicon oxide layer of a pre-determined thickness. Then, a photoresist layer is coated on the silicon oxide layer. After an exposing process, a pre-determined latent pattern is formed in the photoresist layer. Finally, after a developing process, the pre-determined latent pattern of the photoresist is removed so as to expose corresponding portions of the silicon oxide layer underneath the latent pattern of the photoresist layer. As a result, the present invention solves a problem that fluorine ions in the fluorine silicate glass layer 24 diffuse to a surface of the fluorine silicate glass layer 24 to combine with water to form hydrofluoric acid, that contaminates the photoresist and leads to reliability issues.

Abstract translation: 本发明示出了在氟硅玻璃膜上进行表面处理的方法。 首先，在半导体晶片上沉积氟硅酸盐玻璃层。 氟硅玻璃层中的部分氟离子被原位去除以形成预定厚度的氧化硅层。 然后，将光致抗蚀剂层涂覆在氧化硅层上。 在曝光处理之后，在光致抗蚀剂层中形成预定的潜像。 最后，在显影处理之后，去除光致抗蚀剂的预定潜在图案，以暴露在光致抗蚀剂层的潜在图案之下的氧化硅层的相应部分。 结果，本发明解决了氟硅玻璃层24中的氟离子扩散到氟硅酸盐玻璃层24的表面，与水结合形成氢氟酸的问题，污染光致抗蚀剂并导致可靠性问题。

公开(公告)号：US06429152B1

公开(公告)日：2002-08-06

申请号：US09885043

申请日：2001-06-21

Applicant: Neng-Hui Yang ,  Ming-Sheng Yang

Inventor： Neng-Hui Yang ,  Ming-Sheng Yang

IPC: H01L21477

CPC classification number: H01L21/02123 ,  C23C16/0245 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31612

Abstract: A method is given to form a thin film on a surface of a semiconductor wafer. The surface has at least a first region, containing an inner portion of the wafer, and a second region, containing an outer portion of the wafer, and slopes outward from the first region to the second region. The method starts with performing an in-situ inert gas plasma treatment on the surface of the semiconductor wafer to generate different temperatures from the first region to the second region. Different deposition rates of a precursor A from the first region to the second region are thus generated so as to form a flat surface. Then a precursor A-chemical vapor deposition (CVD) process is performed to form the thin film with the flat surface immediately after performing the inert gas plasma treatment.

Abstract translation: 给出了在半导体晶片的表面上形成薄膜的方法。 所述表面具有至少第一区域，其包含所述晶片的内部部分，以及第二区域，所述第二区域包含所述晶片的外部部分，并且从所述第一区域向外倾斜到所述第二区域。 该方法开始于在半导体晶片的表面上进行原位惰性气体等离子体处理，以从第一区域到第二区域产生不同的温度。 因此，产生从第一区域到第二区域的前体A的不同沉积速率，以形成平坦表面。 然后在进行惰性气体等离子体处理之后立即进行前体A化学气相沉积（CVD）工艺以形成具有平坦表面的薄膜。

公开(公告)号：US07306681B2

公开(公告)日：2007-12-11

申请号：US10843444

申请日：2004-05-12

Applicant: Ya-Lun Cheng ,  Yi-Chia Lee ,  Yu-Ren Wang ,  Neng-Hui Yang

Inventor： Ya-Lun Cheng ,  Yi-Chia Lee ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: B08B3/00

CPC classification number: H01L21/02052 ,  B08B3/08 ,  C11D3/3942 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  Y10S438/906

Abstract: A cleaning method and cleaning recipes are disclosed. The present invention relates to a method for cleaning a semiconductor substrate and cleaning recipes. The present invention utilizes a first cleaning solution including diluted hydrofluoric acid and a second cleaning solution including hydrogen chloride and hydrogen peroxide (H2O2) to clean a semiconductor substrate without using an alkaline solution including ammonium hydroxide. Accordingly, a clean surface of a semiconductor substrate is provided in selective epitaxial growth (SEG) process to grow an epitaxial layer with smooth surface.

Abstract translation: 公开了一种清洁方法和清洁配方。 本发明涉及一种清洗半导体衬底和清洁配方的方法。 本发明利用包含稀释氢氟酸的第一清洗溶液和包含氯化氢和过氧化氢（H 2 O 2 O 2）的第二清洗溶液来清洁半导体衬底而不使用 包括氢氧化铵的碱性溶液。 因此，在选择性外延生长（SEG）工艺中提供半导体衬底的干净的表面以生长具有光滑表面的外延层。