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    Stacked Chip System
    1.
    发明申请
    Stacked Chip System 有权
    堆叠芯片系统

    公开(公告)号：US20140266418A1

    公开(公告)日：2014-09-18

    申请号：US13835055

    申请日：2013-03-15

    Applicant: Chao-Yuan Huang ,  Yueh-Feng Ho ,  Ming-Sheng Yang ,  Hwi-Huang Chen

    Inventor： Chao-Yuan Huang ,  Yueh-Feng Ho ,  Ming-Sheng Yang ,  Hwi-Huang Chen

    IPC: H01L23/50

    CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

    Abstract translation: 提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV， 多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二 信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及 其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

    Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device
    4.
    发明授权
    Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device 有权
    用于减少集成电路器件中互连之间的不需要的电容耦合的气隙形成方法

    公开(公告)号：US07253095B2

    公开(公告)日：2007-08-07

    申请号：US11179840

    申请日：2005-07-11

    Applicant: Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

    Inventor： Water Lur ,  David Lee ,  Kuang-Chih Wang ,  Ming-Sheng Yang

    IPC: H01L21/4763

    CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

    Abstract translation: 公开了一种气隙结构和形成方法，用于显着减少集成电路器件中的相邻互连，金属线或其他特征之间的不需要的电容。 空气间隙在期望被隔离的互连之上延伸并且还可以另外延伸，从而最小化线之间的边缘场。 集成气隙结构和形成方法可以与镶嵌或常规集成电路金属化方案结合使用。 此外，可以制造多个级别的集成气隙结构以适应多个金属水平，同时始终确保将物理介电层支撑件提供给互连下面的器件结构。

    Light sensing element having two functions
    5.
    发明申请
    Light sensing element having two functions 失效
    光传感元件具有两个功能

    公开(公告)号：US20060132861A1

    公开(公告)日：2006-06-22

    申请号：US11197407

    申请日：2005-08-05

    Applicant: Chih-Hsien Wei ,  Ming-Sheng Yang

    Inventor： Chih-Hsien Wei ,  Ming-Sheng Yang

    IPC: H04N1/04

    CPC classification number: H04N1/00702 ,  H04N1/00681 ,  H04N1/00734 ,  H04N1/00753 ,  H04N1/00761 ,  H04N1/00779 ,  H04N1/047 ,  H04N1/192 ,  H04N1/486 ,  H04N2201/04715

    Abstract: A light sensing element having two functions is provided for a high-speed image scanning system to scan a document, including a set of matrix light-sensing cells for detecting a scanning location for the scanned document, thereby feeding the sensed signals to control the scanning location and scanning speed, and at least one set of trilinear light-sensing cells for sensing an document, thereby acquiring image signals.

    Abstract translation: 提供具有两个功能的感光元件用于高速图像扫描系统以扫描文档，包括用于检测扫描文档的扫描位置的一组矩阵光感测单元，从而馈送感测的信号以控制扫描 位置和扫描速度，以及用于感测文档的至少一组三线感测单元，从而获取图像信号。

    Method of preventing leakage current of a metal-oxide semiconductor transistor
    6.
    发明授权
    Method of preventing leakage current of a metal-oxide semiconductor transistor 有权
    防止金属氧化物半导体晶体管的漏电流的方法

    公开(公告)号：US06723609B2

    公开(公告)日：2004-04-20

    申请号：US10065717

    申请日：2002-11-13

    Applicant: Ming-Sheng Yang ,  Chia-Hung Kao ,  Chin-Cheng Chien

    Inventor： Ming-Sheng Yang ,  Chia-Hung Kao ,  Chin-Cheng Chien

    IPC: H01L21336

    CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.

    Abstract translation: 栅极氧化物层和栅极依次形成在衬底上，此后在衬底中形成源极/漏极延伸部。 然后形成衬层以覆盖衬底，并且在衬垫层上依次形成第一电介质层和第二电介质层。 通过进行蚀刻处理，在栅极的任一侧上形成L形间隔物。 然后去除由L形间隔物覆盖的衬垫层的部分，此后在衬底中同时形成步骤源极/漏极延伸部和源极/漏极。 最后，进行自对准硅化处理以在栅极上以及源极/漏极上方的硅衬底表面的部分上形成硅化物层。

    Method of forming a thin film on a semiconductor wafer
    7.
    发明授权
    Method of forming a thin film on a semiconductor wafer 有权
    在半导体晶片上形成薄膜的方法

    公开(公告)号：US06429152B1

    公开(公告)日：2002-08-06

    申请号：US09885043

    申请日：2001-06-21

    Applicant: Neng-Hui Yang ,  Ming-Sheng Yang

    Inventor： Neng-Hui Yang ,  Ming-Sheng Yang

    IPC: H01L21477

    CPC classification number: H01L21/02123 ,  C23C16/0245 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31612

    Abstract: A method is given to form a thin film on a surface of a semiconductor wafer. The surface has at least a first region, containing an inner portion of the wafer, and a second region, containing an outer portion of the wafer, and slopes outward from the first region to the second region. The method starts with performing an in-situ inert gas plasma treatment on the surface of the semiconductor wafer to generate different temperatures from the first region to the second region. Different deposition rates of a precursor A from the first region to the second region are thus generated so as to form a flat surface. Then a precursor A-chemical vapor deposition (CVD) process is performed to form the thin film with the flat surface immediately after performing the inert gas plasma treatment.

    Abstract translation: 给出了在半导体晶片的表面上形成薄膜的方法。 所述表面具有至少第一区域，其包含所述晶片的内部部分，以及第二区域，所述第二区域包含所述晶片的外部部分，并且从所述第一区域向外倾斜到所述第二区域。 该方法开始于在半导体晶片的表面上进行原位惰性气体等离子体处理，以从第一区域到第二区域产生不同的温度。 因此，产生从第一区域到第二区域的前体A的不同沉积速率，以形成平坦表面。 然后在进行惰性气体等离子体处理之后立即进行前体A化学气相沉积（CVD）工艺以形成具有平坦表面的薄膜。

    Method for gap filling
    8.
    发明授权
    Method for gap filling 有权
    间隙填充方法

    公开(公告)号：US06410446B1

    公开(公告)日：2002-06-25

    申请号：US09531974

    申请日：2000-03-20

    Applicant: Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

    Inventor： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

    IPC: H01L2131

    CPC classification number: H01L21/02164 ,  C23C16/045 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76801 ,  H01L21/76837

    Abstract: A method of filling a gap is proposed. The method of the invention is applied on a substrate which has conductive structures formed thereon. A HDPCVD is performed to form a dielectric layer on the substrate. The HDPCVD process comprises multi-steps. In a first step, a gas source is added to a deposition chamber to form dielectric material over the substrate. The gas source comprises reactive gas and inert gas. Thus, the first step can simultaneously perform deposition and sputtering. In a second step, the reactive gas is driven out of the deposition chamber. Only sputtering is used to remove a part of the dielectric material at top corners of the conductive structures. In a third step, the reactive gas is again added into the deposition chamber to deposit the dielectric material until filling the gap.

    Abstract translation: 提出填补空白的方法。 本发明的方法应用于其上形成有导电结构的基板上。 执行HDPCVD以在衬底上形成电介质层。 HDPCVD过程包括多步骤。 在第一步骤中，将气体源添加到沉积室以在衬底上形成电介质材料。 气源包括反应性气体和惰性气体。 因此，第一步骤可以同时进行沉积和溅射。 在第二步骤中，反应气体被驱出离开沉积室。 仅使用溅射来去除导电结构的顶角处的介电材料的一部分。 在第三步骤中，将反应性气体再次添加到沉积室中以沉积介电材料直到填充间隙。

    Method of forming inter-metal dielectric layer
    9.
    发明授权
    Method of forming inter-metal dielectric layer 有权
    形成金属间介电层的方法

    公开(公告)号：US06376394B1

    公开(公告)日：2002-04-23

    申请号：US09617458

    申请日：2000-07-17

    Applicant: Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

    Inventor： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

    IPC: H01L2101

    CPC classification number: H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834

    Abstract: A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

    Abstract translation: 金属间介电层的制造方法适用于多层互连。 衬底上形成有金属线。 然后在衬底上形成具有低氟含量的第一（氟化硅玻璃）FSG层，随后在第一FSG层上形成偏置夹持的FSG层。 在第二FSG层上形成氧化物覆盖层之前，在偏压夹层上形成具有低氟含量的第二FSG层。 氧化物盖层被平坦化，直到氧化物覆盖层与第二FSG层平齐。

    Method for improving non-uniformity of chemical mechanical polishing by over coating
    10.
    发明授权
    Method for improving non-uniformity of chemical mechanical polishing by over coating 有权
    通过过涂层改善化学机械抛光不均匀的方法

    公开(公告)号：US06344408B1

    公开(公告)日：2002-02-05

    申请号：US09296177

    申请日：1999-04-22

    Applicant: Hsueh-Chung Chen ,  Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

    Inventor： Hsueh-Chung Chen ,  Ming-Sheng Yang ,  Juan-Yuan Wu ,  Water Lur

    IPC: H01L214763

    CPC classification number: H01L21/3212

    Abstract: A method for improving non-uniformity of chemical mechanical polishing by over coating layer is disclosed. The essential point of the invention is that an over coating layer is formed over a surface before the surface is planarized by a chemical mechanical polishing process. Note that polishing rate of the over coating layer must be less than the polishing rate of the surface, where the ratio of polishing rate is called as selectivity. Because the topography of the surface is not uniform, the topography of the over coating layer also is non-uniform and then the polishing probability in different parts of the over coating layer is different. Obviously, when the over coating layer on the higher area part of the surface is totally consumed, these are residual over coating layer on the lower area part of the surface. Thus, over polishing in the lower area part is prevented by residual over coating layer. Before total over coating layer is polished, the polished account of the surface is higher in the high area part and is lower in the lower area part. Thus, uniformity of the surface is enhanced. Moreover, enhancement of uniformity is direct proportional to product of selectivity and depth of over coating layer.

    Abstract translation: 公开了一种通过过涂层改善化学机械抛光不均匀性的方法。 本发明的要点在于，在通过化学机械抛光工艺对表面进行平面化之前，在表面上形成过涂覆层。 注意，涂层的抛光速率必须小于抛光速率比被称为选择性的表面的抛光速率。 由于表面的形貌不均匀，外涂层的形貌也不均匀，在外涂层不同部位的抛光概率不同。 显然，当表面的较高区域部分上的过涂层完全消耗时，这些是在表面的下部区域上的残留涂层。 因此，通过残留的覆盖层来防止在下部区域部分的过度抛光。 在完全涂覆层被抛光之前，表面的抛光量在高面积部分较高，下部区域较低。 因此，表面的均匀性增强。 此外，均匀性的增强与涂层的选择性和深度的乘积成正比。

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